參數(shù)資料
型號: IDT82V2048LDAG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 22/48頁
文件大?。?/td> 0K
描述: IC LIU T1/E1 8CH SHORT 144-TQFP
標準包裝: 30
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應商設備封裝: 144-TQFP(20x20)
包裝: 托盤
其它名稱: 82V2048LDAG
29
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
4
IEEE STD 1149.1 JTAG TEST
ACCESS PORT
The IDT82V2048L supports the digital Boundary Scan Specification
as described in the IEEE 1149.1 standards.
The boundary scan architecture consists of data and instruction
registers plus a Test Access Port (TAP) controller. Control of the TAP is
achieved through signals applied to the TMS and TCK pins. Data is
shifted into the registers via the TDI pin, and shifted out of the registers
via the TDO pin. JTAG test data are clocked at a rate determined by
JTAG test clock.
The JTAG boundary scan registers includes BSR (Boundary Scan
Register), IDR (Device Identification Register), BR (Bypass Register)
and IR (Instruction Register). These will be described in the following
pages. Refer to Figure-12 for architecture.
4.1
JTAG INSTRUCTIONS AND INSTRUCTION REG-
ISTER (IR)
The IR with instruction decode block is used to select the test to be
executed or the data register to be accessed or both.
The instructions are shifted in LSB first to this 3-bit register. See
codes and the instructions related.
Figure-12 JTAG Architecture
BSR (Boundary Scan Register)
IDR (Device Identification Register)
BR (Bypass Register)
IR (Instruction Register)
MUX
TDO
TDI
TCK
TMS
TRST
Control<6:0>
MUX
Select
High-Z Enable
TAP
(Test Access Port)
Controller
parallel latched output
Digital output pins
Digital input pins
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