參數(shù)資料
型號： IDT82P2916BFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 52/138頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 16CH SH 484BGA
標(biāo)準(zhǔn)包裝： 84
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 16
電源電壓： 1.8V, 3.3V
功率（瓦特）： 3.10W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-LFBGA
供應(yīng)商設(shè)備封裝： 484-CABGA（19x19）
包裝： 托盤
包括： AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠(yuǎn)程檢測器和發(fā)生器
IDT82P2916
16-CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Pin Description
20
April 24, 2010
JTAG (per IEEE 1149.1)
TRST
Input
Pull-Down
AB8
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. To ensure deterministic operation of the test
logic, TMS should be held high when the signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-down resistor.
TMS
Input
Pull-up
W11
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK. To ensure deterministic operation of the test logic, TMS should be held high when the
signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-up resistor.
TCK
Input
W12
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
When TCK is idle at low state, all stored-state devices contained in the test logic shall retain
their state indefinitely.
This pin should be connected to GNDD when JTAG is not used.
TDI
Input
Pull-up
AA9
TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK. This
pin has an internal pull-up resistor.
This pin may be left unconnected when JTAG is not used.
TDO
Output
AB9
TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO is a High-Z output signal except during the process of data scanning.
Power & Ground
VDDIO
D8, D13, D15, D17, E10, F12, P13,
R10, R11, R16, T7
VDDIO: 3.3 V I/O Power Supply
VDDA
N21, M12, N12, M18
VDDA: 3.3 V Analog Core Power Supply
VDDD
F5, F8, F10, F13, F14, F15, F16,
F17, F18, G5, G6, G11, R12, R14,
R15, T8, T9, T16, U8, U9
VDDD: 1.8 V Digital Core Power Supply
VDDRn
(N=0~15)
H6, J16, K8, K9, K13, K15, L5, L6,
L17, M7, M9, M16, N7, N16, P8,
P17
VDDRn: 3.3 V Power Supply for Receiver
VDDT
J5, J6, J17, J18, K5, K6, K17, K18,
L7, L9, L13, L16, M5, M6, M10,
M17, N5, N6, N13, N15, N17, N18,
P5, P6, R5, R6, T18, T19
VDDT: 3.3 V Power Supply for Transmitter Driver
GNDA
E2, E3, E4, E19, E20, F3, F4, F19,
F20, M13, M21, T3, T4, T20, U3,
U4, U19, U20, V3, V20, V21
GNDA: GND for Analog Core / Receiver
Name
I / O
Pin No.
Description
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