
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Programming Information
126
February 25, 2008
5.1.1.2 Indirect Register
PMON
RCRB
RPLC
TPLC
Address (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Reference Page
00
CRCE7
CRCE6
CRCE5
CRCE4
CRCE3
CRCE2
CRCE1
CRCE0
CRCE Counter Mapping 0
01
-
CRCE9
CRCE8
CRCE Counter Mapping 1
02
FER7
FER6
FER5
FER4
FER3
FER2
FER1
FER0
FER Counter Mapping 0
03
-
FER11
FER10
FER9
FER8
FER Counter Mapping 1
04
-
COFA2
COFA1
COFA0
COFA Counter Mapping
05
-
OOF4
OOF3
OOF2
OOF1
OOF0
OOF Counter Mapping
06
PRGD7
PRGD6
PRGD5
PRGD4
PRGD3
PRGD2
PRGD1
PRGD0
PRGD Counter Mapping 0
07
PRGD15 PRGD14 PRGD13
PRGD12
PRGD11
PRGD10
PRGD9
PRGD8
PRGD Counter Mapping 1
08
LCV7
LCV6
LCV5
LCV4
LCV3
LCV2
LCV1
LCV0
LCV Counter Mapping 0
09
LCV15
LCV14
LCV13
LCV12
LCV11
LCV10
LCV9
LCV8
LCV Counter Mapping 1
0A
DDSE7
DDSE6
DDSE5
DDSE4
DDSE3
DDSE2
DDSE1
DDSE0
DDSE Counter Mapping 0
0B
-
DDSE9
DDSE8
DDSE Counter Mapping 1
Address (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Reference Page
01 ~ 18
-
EXTRACT
A
B
C
D
Extracted Signaling Data/Extract
Enable Register for CH1 ~ CH24
Address (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Reference Page
01 ~ 18
SUBST2 SUBST1 SUBST0
SINV
OINV
EINV
G56K
GAP
Channel Control Register for
CH1 ~ CH24
21 ~ 38
DTRK7
DTRK6
DTRK5
DTRK4
DTRK3
DTRK2
DTRK1
DTRK0
Data Trunk Conditioning Code
Register for CH1 ~ CH24
41 ~ 58
-
TEST
-
STRKE
N
A
B
C
D
Signaling Trunk Conditioning
Code Register for CH1 ~ CH24
Address
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Reference Page
01 ~ 18
SUBST2
SUBST1
SUBST0
SINV
OINV
EINV
G56K
GAP
Channel Control Register for
CH1 ~ CH24
21 ~ 38
DTRK7
DTRK6
DTRK5
DTRK4
DTRK3
DTRK2
DTRK1
DTRK0
Data Trunk Conditioning Code
Register for CH1 ~ CH24
41 ~ 58
-
TEST
SIGINS
STRKE
N
A
B
C
D
Signaling Trunk Conditioning
Code Register for CH1 ~ CH24