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參數(shù)資料
| 型號： | IDT82P2282PFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 346/381頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX T1/J1/E1 2CH 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 82P2282PFG IDT82P2282PFG-ND |
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
67
August 20, 2009
Figure 20. T1/J1 To E1 Format Mapping - Continuous Channels Mode
In the Receive Clock Slave mode, the timing signal on the RSCKn
pin and the framing pulse on the RSFSn pin to output the data on the
RSDn pin are provided by the system side. When the RSLVCK bit is set
to ‘0’, each link uses its own RSCKn and RSFSn; when the RSLVCK bit
is set to ‘1’ and both two links are in the Receive Clock Slave mode, the
two links use the RSCK[1] and RSFS[1] to output the data. The signaling
bits on the RSIGn pin are per-channel aligned with the data on the
RSDn pin.
In the Receive Clock Slave mode, the data on the system interface
is clocked by the RSCKn. The active edge of the RSCKn used to sample
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead. The data rate of the system side is 1.544 Mb/s
or 2.048 Mb/s. When it is 2.048 Mb/s, the RSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
MHz) or double the data rate (4.096 MHz). If both two links use the
RSCK[1] and RSFS[1] to output the data, the CMS bit of the two links
should be set to the same value. If the speed of the RSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to update the data on the
RSDn and RSIGn pins. The pulse on the RSFSn pin is always sampled
on its first active edge.
In the Receive Clock Slave mode, the RSFSn asserts at a rate of
integer multiple of 125
s to indicate the start of a frame. The active
polarity of the RSFSn is selected by the FSINV bit. If the pulse on the
RSFSn pin is not an integer multiple of 125
s, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.1.3
Receive Multiplexed Mode
In the Receive Multiplexed mode, since the received data from the
two links should be mapped to 2.048 Mb/s format first, the 3 kinds of
schemes should be selected by the MAP[1:0] bits. The mapping per
G.802, per One Filler Every Four CHs and per Continuous CHs are the
same as the description in Chapter 3.17.1.2 Receive Clock Slave Mode.
In the Receive Multiplexed mode, a multiplexed bus is used to out-
put the data from both two links. The data of Link 1 to Link 2 is byte-
interleaved output on the multiplexed bus. When the data from the two
links is output on one multiplexed bus, the sequence of the data is
arranged by setting the channel offset. The data from different links on
one multiplexed bus must be shifted at a different channel offset to avoid
data mixing.
In the Receive Multiplexed mode, the timing signal on the MRSCK
pin and the framing pulse on the MRSFS pin are provided by the system
side and common to both two links. The signaling bits on the MRSIG pin
are per-channel aligned with the corresponding data on the MRSD pin.
In the Receive Multiplexed mode, the data on the system interface
is clocked by the MRSCK. The active edge of the MRSCK used to sam-
ple the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSD and MRSIG
is determined by the DE bit. The FE bit and the DE bit of the two links
should be set to the same value respectively. If the FE bit and the DE bit
are not equal, the pulse on the MRSFS is ahead. The MRSCK can be
selected by the CMS bit to be the same rate as the data rate on the sys-
tem side (8.192 MHz) or double the data rate (16.384 MHz). The CMS
bit of the two links should be set to the same value. If the speed of the
MRSCK is double the data rate, there will be two active edges in one bit
duration. In this case, the EDGE bit determines the active edge to
update the data on the MRSD and MRSIG pins. The pulse on the
MRSFS pin is always sampled on its first active edge.
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
integer multiple of 125
s to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. The FSINV bit of the
two links should be set to the same value. If the pulse on the MRSFS pin
is not an integer multiple of 125
s, this detection will be indicated by the
RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will be reported
by the INT pin when the RCOFAI bit is ‘1’.
3.17.1.4
Offset
Bit offset and channel offset are both supported in all the operating
modes. The offset is between the framing pulse on RSFSn/MRSFS pin
and the start of the corresponding frame output on the RSDn/MRSD pin.
The signaling bits on the RSIGn/MRSIG pin are always per-channel
aligned with the data on the RSDn/MRSD pin.
1.544
Mb/s
2.048
Mb/s
CH1
CH2
CH3
F
CH23
CH1
CH2
CH24
TS0
TS2
TS1
TS23
TS24
TS0
TS1
TS2
TS24
the 8th bit
CH24
TS3
TS25~TS31
the 8th bit
F
F CH1
filler
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| IDT82P2282PFG8 | 功能描述:TXRX T1/J1/E1 2CHAN 100-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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| IDT82P2282PK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Dual T1/E1/J1 Long Haul / Short Haul Transceiver |
| IDT82P2284 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Quad T1/E1/J1 Long Haul / Short Haul Transceiver |
| IDT82P2284BB | 功能描述:TXRX T1/J1/E1 4CHAN 208-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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