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  • 參數(shù)資料
    型號(hào): IDT79RC32T351-100DHG
    廠商: IDT, Integrated Device Technology Inc
    文件頁(yè)數(shù): 2/42頁(yè)
    文件大?。?/td> 0K
    描述: IC MPU 32BIT CORE 100MHZ 208-QFP
    產(chǎn)品變化通告: Product Discontinuation 07/Dec/2009
    標(biāo)準(zhǔn)包裝: 24
    系列: Interprise™
    處理器類型: RISC 32-位
    速度: 100MHz
    電壓: 2.5V
    安裝類型: 表面貼裝
    封裝/外殼: 208-BFQFP
    供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
    包裝: 托盤(pán)
    其它名稱: 79RC32T351-100DHG
    10 of 42
    May 25, 2004
    IDT 79RC32351
    EJTAG_TRST_N
    I
    STI
    EJTAG Test Reset. EJTAG_TRST_N is an active-low signal for asynchronous reset of only the EJTAG/ICE controller.
    EJTAG_TRST_N requires an external pull-up on the board. EJTAG/ICE enable is selected during reset using the boot con-
    figuration and overrides the selection of the Primary and Alternate functions. This signal requires an external resistor, listed
    Primary: General Purpose I/O, GPIOP[31]
    1st Alternate function: DMA finished output, DMAFIN.
    JTAG_TRST_N
    I
    STI
    JTAG Test Reset. JTAG_TRST_N is an active-low signal for asynchronous reset of only the JTAG boundary scan control-
    ler. JTAG_TRST_N requires an external pull-down on the board that will hold the JTAG boundary scan controller in reset
    when not in use if selected. JTAG reset enable is selected during reset using the boot configuration and overrides the
    selection of the Primary and Alternate functions.
    Primary function: General Purpose I/O, GPIOP[2].
    1st Alternate function: UART channel 0 ring indicator, U0RIN.
    Debug
    INSTP
    O
    Low Drive Instruction or Data Indicator. This signal is driven high during CPU instruction fetches and low during CPU data transac-
    tions on the memory and peripheral bus.
    CPUP
    O
    Low Drive CPU or DMA Transaction Indicator. This signal is driven high during CPU transactions and low during DMA transactions
    on the memory and peripheral bus if CPU/DMA Transaction Indicator Enable is enabled. CPU/DMA Status mode enable is
    selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions.
    Primary function: General Purpose I/O, GPIOP[4].
    1st Alternate function: UART channel 0 data terminal ready U0DTRN.
    DMAP[0]
    O
    Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the
    selection of the Primary and Alternate functions.
    Primary function: General Purpose I/O, GPIOP[23].
    1st Alternate function: TXADDR[1].
    DMAP[1]
    O
    Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the
    selection of the Primary and Alternate functions.
    Primary function: General Purpose I/O, GPIOP[25].
    1st Alternate function: RXADDR[1].
    DMAP[2]
    O
    Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the
    selection of the Primary and Alternate functions.
    Primary function: General Purpose I/O, GPIOP[9].
    1st Alternate function: U1SINP.
    DMAP[3]
    O
    Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the
    selection of the Primary and Alternate functions.
    Primary function: General Purpose I/O, GPIOP[8].
    1st Alternate function: U1SOUTP.
    UART
    U0SOUTP
    I
    STI
    UART channel 0 serial transmit.
    Primary function: General Purpose I/O, GPIOP[0]. At reset, this pin defaults to primary function GPIOP[0].
    U0SINP
    I
    STI
    UART channel 0 serial receive.
    Primary function: General Purpose I/O, GPIOP[1]. At reset, this pin defaults to primary function GPIOP[1].
    U0RIN
    I
    STI
    UART channel 0 ring indicator.
    Primary function: General Purpose I/O, GPIOP[2]. At reset, this pin defaults to primary function GPIOP[2] if JTAG reset
    enable is not selected during reset using the boot configuration.
    2nd Alternate function: JTAG boundary scan reset, JTAG_TRST_N.
    U0DCRN
    I
    STI
    UART channel 0 data carrier detect.
    Primary function: General Purpose I/O, GPIOP[3]. At reset, this pin defaults to primary function GPIOP[3].
    Name
    Type I/O Type
    Description
    Table 1 Pin Descriptions (Part 6 of 7)
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