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參數(shù)資料
| 型號： | IDT79RC32T336-150BCG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 34/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT CORE 150MHZ 256-BGA |
| 標準包裝： | 90 |
| 系列： | Interprise™ |
| 處理器類型： | MIPS32 32-位 |
| 速度： | 150MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CABGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | 79RC32T336-150BCG |
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October 4, 2005
RC32336
P
PP
Pin Description Table
in Description Table
The following table lists the functions of the pins provided on the RC32336. Some of the functions listed may be multiplexed onto the same pin
(indicated as alternate functions).
To define the active polarity of a signal, a suffix will be used. Signals ending with an “N” should be interpreted as being active, or asserted, when at
a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one
(high) level.
Signal
Type
Name/Description
Memory and Peripheral Bus
BDIRN
O
External Buffer Direction. Memory and peripheral bus external data bus buffer direction control.
If the RC32336 memory and peripheral bus is connected to the A side of a transceiver such as an
IDT74FCT245, then this pin may be directly connected to the direction control (e.g., BDIR) pin of
the transceiver.
BOEN[1:0]
O
External Buffer Enable. These signals provide output enable control for external buffers on the
memory and peripheral data bus.
BWEN[3:0]
O
Byte Write Enables. These signals are memory and peripheral bus byte write enable signals.
BWEN[0] corresponds to byte lane MDATA[7:0]
BWEN[1] corresponds to byte lane MDATA[15:8]
BWEN[2] corresponds to byte lane MDATA[23:16]
BWEN[3] corresponds to byte lane MDATA[31:24]
During PC Card accesses the BWEN[0] acts as the PC Card memory output enable (OE#) signal
and BWEN[1] acts as the PC Card memory write enable (WE#) signal.
CSN[5:0]
O
Chip Selects. These signals are used to select an external device on the memory and peripheral
bus.
MADDR[21:0]
O
Address Bus. 22-bit memory and peripheral bus address bus.
MADDR[25:22] are available as GPIO[5:2] alternate functions.
MDATA[31:0]
I/O
Data Bus. 32-bit memory and peripheral data bus. During a cold reset, bits 0 through 16 of this
data bus function as inputs that are used to load the boot configuration vector.
OEN
O
Output Enable. This signal is asserted when data should be driven by an external device on the
memory and peripheral bus.
RWN
O
Read Write. This signal indicates whether the transaction on the memory and peripheral bus is a
read transaction or a write transaction. A high level indicates a read from an external device. A
low level indicates a write to an external device.
WAITACKN
I
Wait or Transfer Acknowledge. When configured as wait, this signal is asserted during a mem-
ory and peripheral bus transaction to extend the bus cycle. When configured as a transfer
acknowledge, this signal is asserted during a transaction to signal the completion of the transac-
tion.
RASN
O
SDRAM Row Address Strobe. Row address strobe asserted during memory and peripheral bus
SDRAM transactions.
CASN
O
SDRAM Column Address Strobe. Column address strobe asserted during memory and periph-
eral bus SDRAM transactions.
SDCSN[1:0]
O
SDRAM Chip Selects. These signals are used to select SDRAM device(s) on the memory and
peripheral bus.
SDWEN
O
SDRAM Write Enable. This signal is asserted during memory and peripheral bus SDRAM write
transactions.
SDCLKOUT
O
SDRAM Clock Output. This clock is used for all SDRAM memory and peripheral bus operations.
Table 1 Pin Description (Part 1 of 6)
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