參數(shù)資料
型號： IDT77V500S25PF8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 4/17頁
文件大?。?/td> 0K
描述： IC SW MEMORY 8X8 1.2BGPS 100TQFP
標(biāo)準(zhǔn)包裝： 750
系列： SwitchStar™
類型： 集成式開關(guān)控制器
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 77V500S25PF8
12 of 17
April 11, 2001
IDT77V500
CBR Clock Functional Waveform Example 1 - CBR Frame Implementation
(Fast CBRCLK with Frame Timing)
This example shows the procedure recommended for use of direct CBR scheduling. "x" for this waveform represents either 2 or 3, depending on
which CBRCLK is used (CBRCLK2 or CBRCLK3) ("y" represents the specific output (0-7)). The OPyCBRx VC List for this example is defined in Figure
1A cell from a VC on the OPyCBRx VC List is scheduled on each rising clock edge of SCLK after a falling edge of CBRCLKx if the previous VC has completed internal processing.
2This example shows four VCs in the OPyCBRx VC List. The number of VCs in the OPxCBRx VC List may be as large as 8192.
3The period between reinitiation of the OPyCBRx VC List defines the frame size; that is, the amount of time between starting the transmissions from the top of the OPyCBRx VC List.
CBRCLKx must be HIGH for eight clocks or more to reinitiate the transmission sequence at the start of the OPyCBRx VC List.
CBR Clock Functional Waveform Example 2 - VBR/CBR Implementation
(t
(tCH
CH
x > 8 SCLK)
This example shows the use of a slower CBRCLK (tCHx > 8 SCLK) to provide VBR/CBR traffic shaping. For this waveform "x" represents either 2
or 3, depending on which CBRCLK is used (CBRCLK2 or CBRCLK3). ("y" represents the specific output (0-7)) The OPyCBRx VC List for this example
is defined in Figure 3.
1A cell from a VC on the OPyCBRx VC List is scheduled on each rising edge of SCLK after a falling edge of CBRCLKx.
2tCHx > 8 SCLK so that a cell is scheduled after each falling edge of CBRCLKx.
3The pointer has moved back to the beginning of the OPyCBRx VC List.
Reset Waveforms
1RESETI must be held HIGH for 8 SCLK cycles. When RESETI goes Low again 8191 cycles are used prior to the Status Acknowledge bits showing the internal reset process is com-
plete.
2This delay should typically be much less than two SCLK cycles. RESETO remains High until START Command is received from the Call Setup Manager.
12
SCLK
CBRCLKx
100
200
300
400
3
100
200
300
400
12
3607 drw 12
100
SCLK
2
cont'd
waveform
CBRCLKx
1
see cont'd
waveform
3607 drw 13
3
200
300
100
400
SCLK
RESETI
3607 drw 14
1
2
781
2
8190
8191
1
tRSI
RESETO
1
2
2 clock cycles max.
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