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參數(shù)資料
| 型號： | IDT77010L155PQF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Data Path Interface to Utopia Level 1 Translation Device |
| 中文描述： | 數(shù)據(jù)通道接口的烏托邦1級轉(zhuǎn)換設備 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 141K |
| 代理商： | IDT77010L155PQF |
7 of 21
June 24, 2002
IDT77010
UTOPIA Rec eive Interfac e Operation
UTOPIA celllevelhandshakeis usedtoreceiveanATMcellfroma
UTOPIA PHY device. The UTOPIA Receive Clock (RCLK) is a contin-
uous clockgeneratedfromtheSystemClock(SYSCLK) andis halfthe
frequencyoftheDPIReceiveClock(DRxCLK).
The receive cell header, including the HEC, andpayloadare trans-
ferredoverthe Receive Data bus (RxDATA[7:0]), whichis 8-bits wide.
Receive Parity (RxPRTY) is not supported by the 77010, nor does it
calculatetheHEC intheheaderfield.
The77010will assertReceive Enable(RENB) lowtwoclock cycles
after detecting a high Receive Cell Available (RCLAV), if it is not
executing a control cell. Refer to the UTOPIA Receive Flow Control
sectionfordescriptiononmuxing internally generatedcontrol cells with
UTOPIAreceivecells.
Once Receive Start Of Cell (RSOC) is detected the 77010 will
receivetheentirecellwithoutinterruption.
UTOPIA Rec eive Flow Control
The UTOPIA data rate is higherthan the cell rate onthe transport
media. This provides additional bandwidth for the insertion of control
cells.
The 77010 will only generate an internal control cell when RCLAV
andRENBarede-assertedandacelltransferisnottakingplace.When
acontrolcellis insertedRENBis de-assertedhighfor55RCLK cycles,
which prevents the PHY fromtransferring a cell. During this 55 clock
period the 77010 inserts the control cell and sends it out to the DPI
receiveinterface.
Internallygeneratedcontrolcellsshouldbepacedsothatthesumof
receiveUTOPIAstatuscellsandinternallygeneratedcontrolcellsdonot
exceed160Mbps.
ThePHY is expectedtobufferatleasttworeceivecells forthe flow
controltofunctionwithouttheloss ofacell. Figure4shows thereceive
cellmuxingwiththeinternallygeneratedstatuscells.
UTOPIA Transmit Interfac e
Operation
UTOPIA cell level handshake is used to transfer an ATMcell to a
UTOPIA PHY device. The UTOPIA TransmtClock (TCLK) is a contin-
uous clockgeneratedfromtheSystemClock(SYSCLK) andis halfthe
frequencyoftheDPITransmtClock(DTxCLK).
Two TCLK cycles after detection of a high Transmt Cell Available
(TCLAV) the 77010will assertTENB low One TCLK cycle afterTENB
assertionthe 77010 will assert Transmt Start Of Cell (TSOC) andthe
firstvalidbyteofdata.TSOC isoneTCLK cyclelongandcoincideswith
thefirstvalidbyteofdata(TxDATA[7:0]). Whentheentirecellhas been
transferredthe77010willsampleTCLAV forcellavailability.
The PHY will de-assertTCLAV if itcannotacceptanothercell. The
77010 will continue transferring the current cell and store up to nine
bytesofthenextcellinitspipelineifTCLAV is de-assertedduringacell
transfer.
Controlcells fromtheDPIinterfacearefilteredandnotforwardedto
thetransmtUTOPIAbus.
Figure5showsUTOPIAtransmtdataflow
Figure4 UTOPIA ReceiveDataFlow
Figure5 UTOPIA TransmitDataFlow
Line Card Interface
Internally
generated status
cell
Receive DPI bus
4
UTOPIA
Receive Bus
PHY
No back to back
Rx cell detector
4308 drw 05
8
UTOPIA
Interface
Control cell
filter
4 to 8
Interface
DPI
TxCLK
Control
PHY
UTOPIA
Transmit bus
TCLAV
8
4
Transmit DPI bus
Transmit DPI clock
4308 drw 06
UTOPIA
Interface
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT77105L25TFI | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT77155L155PX | 制造商:INT_DEV_TECH 功能描述: |
| IDT77201L25PF | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT77211L155PQF | 制造商:Integrated Device Technology Inc 功能描述:ATM/SONET SEGMENTATION AND REASSEMBLY CIRCUIT, 208 Pin, Plastic, QFP |
| IDT77V011L155DA | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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