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參數(shù)資料
| 型號： | IDT74SSTUBF32865ABKG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER 28BIT 1:2 REG 160-BGA |
| 標準包裝： | 2,000 |
| 邏輯類型： | 1:2 寄存緩沖器，帶奇偶位 |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 位數(shù)： | 28 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-LFBGA |
| 供應商設備封裝： | 160-CABGA（9x13） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 74SSTUBF32865ABKG8 |
IDT74SSTUBF32865A
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE GRADE
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
4
IDT74SSTUBF32865A
7092/11
Ball Assignment
Signal Group
Signal Name
Type
Description
Ungated Inputs
DCKE0, DCKE1,
DODT0, DODT1
SSTL_18
DRAM function pins not associated with Chip Select.
Chip Select Gated
Inputs
D0 ... D21
SSTL_18
DRAM inputs, re-driven only when Chip Select is
LOW.
Chip Select Inputs
DCS0, DCS1
SSTL_18
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one
will be low when a valid address/command is present.
The register can be programmed to re-drive all
D-inputs only (CSGateEN high) when at least one
Chip Select input is LOW.
Re-Driven
Q0A...Q21A,
Q0B...Q21B,
QCSnA,B
QCKEnA,B,
QODTnA,B
SSTL_18
Outputs of the register, valid after the specified clock
count outputs and immediately following a rising edge
of the clock.
Parity Input
PARIN
SSTL_18
Input parity is received on pin PARIN and should
maintain odd parity across the D0...D21 inputs, at the
rising edge of the clock.
Parity Error
PTYERR
Open Drain
When LOW, this output indicates that a parity error
was output identified associated with the address
and/or command inputs. PTYERR will be active for
two clock cycles, and delayed by an additional clock
cycle for compatibility with final parity out timing on
the industry-standard DDR-II register with parity (in
JEDEC definition).
Program Inputs
CSGateEN
1.8V LVCMOS
Chip Select Gate Enable. When HIGH, the D0..D21
inputs will be latched only when at least one Chip
Select input is LOW during the rising edge of the
clock. When LOW, the D0...D21 inputs will be latched
and redriven on every rising edge of the clock.
Clock Inputs
CLK, CLK
SSTL_18
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the
positive clock input (CLK).
Miscellaneous
Inputs
MCL, MCH
Must be connected to a logic LOW or HIGH.
RESET
SSTL_18
Asynchronous reset input. When LOW, it causes a
reset of the internal latches, thereby forcing the
outputs LOW. RESET also resets the PTYERR
signal.
VREF
0.9V nominal
Input reference voltage for the SSTL_18 inputs. Two
pins (internally tied together) are used for increased
reliability.
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