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參數(shù)資料
| 型號(hào)： | IDT74LVC169AQ |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16 |
| 封裝： | QSOP-16 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 103K |
| 代理商： | IDT74LVC169AQ |
7
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVC169A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT UP/DOWN
Open
V LOAD
GN D
VCC
Pulse
Generator
D.U.T.
500
C L
R T
VIN
VOUT
(1, 2)
LVC Q U AD Link
IN PU T
VIH
0V
VOH
V OL
tPLH1
tSK (x)
OU TPU T 1
OU TPU T 2
tPHL1
tSK (x)
tPLH2
tPHL2
VT
V OH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LV C Q U A D Link
DA TA
IN PU T
0V
tREM
TIM IN G
IN P U T
AS YN C H RO N O U S
CO NTR OL
S YNC HRO N O U S
CO NTR OL
tSU
tH
tSU
tH
V IH
VT
V IH
VT
V IH
VT
V IH
VT
LO W -H IGH -LOW
PU LS E
H IGH -LOW -H IGH
PU LSE
VT
tW
SAM E P H AS E
IN PU T TR AN SITIO N
O PPO SITE P H AS E
IN PU T TR AN SITIO N
0V
VOH
VOL
tPLH
tPHL
tPLH
OU TPU T
VT
VIH
VT
VIH
VT
CO N TRO L
IN PU T
tPLZ
0V
OU TPU T
NO RM A LLY
LOW
tPZH
0V
SW IT CH
CLO SED
OU TPU T
NO RM ALLY
HIGH
EN A BLE
D ISA BLE
SW ITC H
OP EN
tPHZ
0V
VLZ
V OH
VT
tPZL
VLOAD/2
VIH
VT
VOL
V HZ
LV C Q U A D Link
LVC Q U AD Link
LV C Q U A D L in k
LV C Q U A D Link
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
OUTPUT SKEW - tsk (x)
PULSE WIDTH
Symbol
VCC(1)= 2.5V ±0.2V
VCC(2)= 3.3V ±0.3V & 2.7V
Unit
VLOAD
2 x Vcc
6
V
VIH
Vcc
2.7
V
VT
VCC / 2
1.5
V
VLZ
150
300
mV
VHZ
150
300
mV
CL
30
50
pF
LVC QUAD Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
DEFINITIONS:
CL=
Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
2. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High
GND
All Other tests
Open
LVC QUAD Link
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