參數(shù)資料
型號(hào): IDT74FCT827BTLB
廠商: Integrated Device Technology, Inc.
英文描述: 3.3V, Low-Noise Phase-Locked Loop Clock Driver with 9 Clock Outputs
中文描述: 快速CMOS 10位緩沖器
文件頁(yè)數(shù): 5/7頁(yè)
文件大小: 127K
代理商: IDT74FCT827BTLB
IDT54/74FCT827AT/BT/CT/DT, IDT54/74FCT2827AT/BT/CT
HIGH-PERFORMANCE CMOS BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.22
5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT827AT/FCT2827AT
FCT827BT/FCT2827BT
Com'l.
Mil.
Com'l.
Mil.
Symbol
t
PLH
t
PHL
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(3)
R
L
= 500
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(3)
R
L
= 500
C
L
= 5pF
(3)
R
L
= 500
C
L
= 50pF
R
L
= 500
Min.
(2)
1.5
Max.
8.0
Min.
(2)
1.5
Max.
9.0
Min.
(2)
1.5
Max.
5.0
Min.
(2)
1.5
Max.
6.5
Unit
ns
Propagation Delay
D
I
to Y
I
1.5
15.0
1.5
17.0
1.5
13.0
1.5
14.0
t
PZH
t
PZL
Output Enable Time
OE
I
to Y
I
1.5
12.0
1.5
13.0
1.5
8.0
1.5
9.0
ns
1.5
23.0
1.5
25.0
1.5
15.0
1.5
16.0
t
PHZ
t
PLZ
Output Disable Time
OE
I
to Y
I
1.5
9.0
1.5
9.0
1.5
6.0
1.5
7.0
ns
1.5
10.0
1.5
10.0
1.5
7.0
1.5
8.0
2573 tbl 09
NOTES
:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These conditions are guaranteed but not tested.
2573 tbl 10
FCT827CT/FCT2827CT
FCT827DT
Com'l.
Mil.
Com'l.
Mil.
Symbol
t
PLH
t
PHL
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(3)
R
L
= 500
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(3)
R
L
= 500
C
L
= 5pF
(3)
R
L
= 500
C
L
= 50pF
R
L
= 500
Min.
(2)
1.5
Max.
4.4
Min.
(2)
1.5
Max.
5.0
Min.
(2)
1.5
Max.
3.8
Min.
(2)
Max.
Unit
ns
Propagation Delay
D
I
to Y
I
1.5
10.0
1.5
11.0
1.5
7.5
t
PZH
t
PZL
Output Enable Time
OE
I
to Y
I
1.5
7.0
1.5
8.0
1.5
5.0
ns
1.5
14.0
1.5
15.0
1.5
9.0
t
PHZ
t
PLZ
Output Disable Time
OE
I
to Y
I
1.5
5.7
1.5
6.7
1.5
4.3
ns
1.5
6.0
1.5
7.0
1.5
4.3
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