參數(shù)資料
型號(hào)： IDT74FCT2827BTEB
廠商： Integrated Device Technology, Inc.
英文描述： 3.3V, 80 to134 MHz, 1 Output Zero-Delay Clock Driver
中文描述： 快速CMOS 10位緩沖器
文件頁(yè)數(shù)： 6/7頁(yè)
文件大?。?/td> 127K
代理商： IDT74FCT2827BTEB
IDT54/74FCT827AT/BT/CT/DT, IDT54/74FCT2827AT/BT/CT
HIGH-PERFORMANCE CMOS BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.22
6
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
SWITCH POSITION
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
2573 lnk 11
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
2573 drw 04
2573 drw 05
2573 drw 06
2573 drw 07
2573 drw 08
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