參數(shù)資料
型號: IDT74FCT16823BTPV8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線收發(fā)器
英文描述: FCT SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56
封裝: SSOP-56
文件頁數(shù): 5/8頁
文件大?。?/td> 82K
代理商: IDT74FCT16823BTPV8
5
IDT54/74FCT16823AT/BT/CT/ET
FAST CMOS 18-BIT REGISTER
MILITARYANDINDUSTRIALTEMPERATURERANGES
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
FCT16823AT
FCT16823BT FCT16823CT
FCT16823ET
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2) Max.
Min.(2)
Max.
Unit
tPLH
Propagation Delay
CL = 50pF
1.5
10
1.5
7.5
1.5
6
1.5
4.4
ns
tPHL
CLK to xQx
RL = 500
CL = 300pF(5)
1.5
20
1.5
15
1.5
12.5
1.5
8
RL = 500
tPHL
Propagation Delay
CL = 50pF
1.5
14
1.5
9
1.5
6.1
1.5
4.4
ns
xCLR to xQx
RL = 500
tPHZ
Output EnableTime
CL = 50pF
1.5
12
1.5
8
1.5
5.5
1.5
4.4
ns
tPLZ
xOE to xQx
RL = 500
CL = 300pF(5)
1.5
23
1.5
15
1.5
12.5
1.5
9
ns
RL = 500
tPHZ
Output Disable Time
CL = 5pF(5)
1.5
7
1.5
6.5
1.5
5.2
1.5
3.6
ns
xOE to xQx
RL = 500
CL = 50pF)
1.5
8
1.5
7.5
1.5
6.5
1.5
3.6
ns
RL = 500
tSU
Set-up Time HIGH or LOW, xDx to xCLK
CL = 50pF
3
3
2
1.5
ns
tH
Hold Time HIGH or LOW, xDx to xCLK
RL = 500
1.5
1.5
1.5
0
ns
tSU
Set-up Time HIGH or LOW, xCLKEN to xCLK
3
3
3
2.5
ns
tH
Hold Time HIGH or LOW, xCLKEN to xCLK
0
0
0
0
ns
tW
xCLK Pulse Width HIGH or LOW
6
6
3.3
3(4)
—ns
tW
xCLR Pulse Width LOW
6
6
3.3
3(4)
—ns
tREM
Recovery Time xCLR to xCLK
6
6
6
3
ns
tSK(o)
Output Skew(3)
0.5
0.5
0.5
0.5
ns
相關(guān)PDF資料
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IDT74FCT16823ETPF8 FCT SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56
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