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參數資料
| 型號： | IDT74FCT166H244ETPF |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | FAST CMOS 16-BIT BUFFER/LINE DRIVER |
| 中文描述： | 快速CMOS 16位緩沖/線路驅動器 |
| 文件頁數： | 8/9頁 |
| 文件大?。?/td> | 151K |
| 代理商： | IDT74FCT166H244ETPF |
IDT54/74FCT16244T/AT/CT/ET, 162244T/AT/CT/ET,
166244T/AT/CT, 162H244T/AT/CT/ET FAST CMOS 16-BIT BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5.2
8
SWITCH POSITION
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2544 lnk 13
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
2544 drw 05
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
2544 drw 07
2544 drw 06
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
2544 drw 09
2544 drw 08
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