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參數(shù)資料
| 型號： | IDT74ALVC74PY |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | ALVC/VCX/A SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | SSOP-14 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 72K |
| 代理商： | IDT74ALVC74PY |
INDUSTRIALTEMPERATURERANGE
IDT74ALVC74
3.3VCMOSDUALPOSITIVEEDGE-TRIGGEREDD-TYPEFLIP-FLOP
1
JUNE 2000
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
DSC-4639/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SOIC, SSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for Heavy Loads
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
IDT74ALVC74
3.3V CMOS DUAL
POSITIVE EDGE-TRIGGERED
D-TYPE FLIP-FLOP WITH
CLEAR AND PRESET
DESCRIPTION:
T
his dual positive-edge-triggered D-type flip-flop is built using advanced
dual metal CMOS technology. A low level at the preset (PRE) or clear (CLR)
inputs sets or resets the outputs, regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the data (D) input meeting
thesetuptimerequirementsistransferredtotheoutputsonthepositive-going
edge of the clock pulse. Clock triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse. Following the hold-time
interval, data at the D input may be changed without affecting the levels at
the outputs.
The ALVC74 has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
TG
C
PRE
CLK
C
TG
C
D
TG
C
TG
C
CLR
Q
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| IDT74ALVCF162835APA | 功能描述:IC UNIV BUS DVR 18BIT 56TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74ALVCF 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標準包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
| IDT74ALVCF162835APA8 | 功能描述:IC UNIV BUS DVR 18BIT 56TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74ALVCF 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標準包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
| IDT74ALVCF162835APAG | 功能描述:IC UNIV BUS DVR 18BIT 56TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74ALVCF 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標準包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
| IDT74ALVCF162835APAG8 | 功能描述:IC UNIV BUS DVR 18BIT 56TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74ALVCF 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標準包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
| IDT74ALVCF162835APF | 功能描述:IC UNIV BUS DVR 18BIT 56TVSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74ALVCF 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標準包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
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