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參數(shù)資料
| 型號： | IDT74ALVC16646PV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.635 MM PITCH, SSOP-56 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 113K |
| 代理商： | IDT74ALVC16646PV |
INDUSTRIALTEMPERATURERANGE
IDT74ALVC16646
3.3VCMOS16-BITBUSTRANSCEIVERANDREGISTERWITH3-STATEOUTPUTS
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4914/2
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
IDT74ALVC16646
3.3V CMOS 16-BIT
BUS TRANSCEIVER
AND REGISTER WITH
3-STATE OUTPUTS
1
D
C1
52
1
B1
5
1
D
C 1
TO SE VEN OTHER CHA N NE LS
1
A1
One of Eight C hannels
1
SAB
1
SBA
1
OE
1
DIR
56
1
55
54
2
3
1
CLKA B
1
CLKBA
1
D
C1
42
2
B1
15
1
D
C1
TO S EVEN OTH E R C H AN N ELS
2
A1
One of Eight C hannels
2
SAB
2
SBA
2
OE
2
DIR
29
28
30
31
27
26
2
CLKA B
2
CLK BA
DESCRIPTION:
This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. TheALVC16646canbeusedastwo8-bittransceiversorone16-
bittransceiver. DataontheAorBbusisclockedintotheregistersonthelow-
to-high transition of the appropriate clock (CLKAB or CLKBA) input.
Output-enable(OE)anddirectioncontrol(DIR)inputsareprovidedtocontrol
the transceiver functions. In the transceiver mode, data present at the high-
impedanceportmaybestoredineitherregisterorboth. Theselectcontrol(SAB
andSBA)inputscanmultiplexstoredandreal-time(transparentmode)data.
Thecircuitryusedforselectcontroleliminatesthetypicaldecodingglitchthat
occursinamultiplexerduringthetransitionbetweenstoredandreal-timedata.
DIRdetermineswhichbusreceivesdatawhenOEislow. Intheisolationmode
(OE high), A data may be stored in one register and/or B data may be stored
intheotherregister. Whenanoutputfunctionisdisabled,theinputfunctionis
still enabled and may be used to store and transmit data. Only one of the two
buses, A or B, can be driven at a time.
TheALVC16646hasbeendesignedwitha±24mAoutputdriver. Thisdriver
is capable of driving a moderate to heavy load while maintaining speed
performance.
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