- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377132 > IDT73ALVCH16823PA (Integrated Device Technology, Inc.) 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD PDF資料下載
參數(shù)資料
| 型號： | IDT73ALVCH16823PA |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| 中文描述： | 3.3V的CMOS 18位總線接口觸發(fā)器具有三態(tài)輸出和總線狀態(tài)保持 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 79K |
| 代理商： | IDT73ALVCH16823PA |
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH16823
3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
ALVC Link
INPUT
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
V
OH
V
T
0V
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
IH
V
T
ALVC Link
DATA
INPUT
TIMING
INPUT
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
t
REM
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
ALVC Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
V
T
ALVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
OPEN
t
PHZ
0V
V
LZ
V
OL
V
OH
V
HZ
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
ALVC Link
TEST CIRCUITS AND WAV EFORMS
TEST CONDITIONS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termnation resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2ns; t
R
≤
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagramshown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc
/ 2
150
150
30
Unit
V
V
V
mV
mV
pF
6
2.7
1.5
300
300
50
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
相關PDF資料 |
PDF描述 |
|---|---|
| IDT74ALVCH16823 | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| IDT83ALVCH16823PA | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| IDT84ALVCH16823PA | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| IDT85ALVCH16823PA | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| IDT42ALVCH16823PA | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74AHCT374D | 制造商:Integrated Device Technology Inc 功能描述:Flip Flop, Octal, D Type, 20 Pin, Ceramic, DIP |
| IDT74ALVC08PG | 制造商:Integrated Device Technology Inc 功能描述:Logic Circuit, Quad 2-Input AND, AVC/ALVC-CMOS, 14 Pin, Plastic, TSSOP |
| IDT74ALVC10AMPG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| IDT74ALVC162244PAG | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器 系列:74ALVC 標準包裝:2,000 系列:74LVCH 邏輯類型:緩沖器/線路驅(qū)動器，非反相 元件數(shù):2 每個元件的位元數(shù):4 輸出電流高，低:24mA，24mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:20-SOIC 包裝:帶卷 (TR) |
| IDT74ALVC162244PAG8 | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器 系列:74ALVC 標準包裝:47 系列:74LVX 邏輯類型:緩沖器/線路驅(qū)動器，非反相 元件數(shù):4 每個元件的位元數(shù):1 輸出電流高，低:4mA，4mA 電源電壓:2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.209"，5.30mm 寬） 供應商設備封裝:14-SOIC 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。