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參數(shù)資料
| 型號： | IDT73720AJ |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 16-BIT TRI-PORT BUS EXCHANGER |
| 中文描述： | 73 SERIES, 16-BIT EXCHANGER, TRUE OUTPUT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 74K |
| 代理商： | IDT73720AJ |
Integrated Device Technology, Inc.
FEATURES:
High-speed 16-bit bus exchange for interbus communica-
tion in the following environments:
— Multi-way interleaving memory
— Multiplexed address and data busses
Direct interface to R3051 family RISChipSet
— R3051
family of integrated RISController
CPUs
— R3721 DRAM controller
Data path for read and write operations
Low noise 12mA TTL level outputs
Bidirectional 3-bus architecture: X, Y, Z
— One CPU bus: X
— Two (interleaved or banked) memory busses:Y & Z
— Each bus can be independently latched
Byte control on all three busses
Source terminated outputs for low noise and undershoot
control
68-pin PLCC and 80-pin PQFP package
High-performance CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
16-BIT TRI-PORT
BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
AUGUST 1995
1995 Integrated Device Technology, Inc.
11.5
DSC-2046/6
1
IDT73720/A
DESCRIPTION:
The IDT73720/A Bus Exchanger is a high speed 16-bit bus
exchange device intended for inter-bus communication in
interleaved memory systems and high performance multi-
plexed address and data busses.
The Bus Exchanger is responsible for interfacing between
the CPU A/D bus (CPU address/data bus) and multiple
memory data busses.
The 73720/A uses a three bus architecture (X, Y, Z), with
control signals suitable for simple transfer between the CPU
bus (X) and either memory bus (Y or Z). The Bus Exchanger
features independent read and write latches for each memory
bus, thus supporting a variety of memory strategies. All three
ports support byte enable to independently enable upper and
lower bytes.
RISChipSet, RISController, R305x, R3051, R3052 are trademarks and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
NOTE:
1. Logic equations for bus control:
OEXU = T/
R
* .
OEU
*; OEXL = T/
R
* .
OEL
*; OEYU = T/
R
. PATH .
OEU
*
OEYL = T/
R
. PATH .
OEL
*; OEZU = T/
R
. PATH* .
OEU
*; OEZL = T/
R
. PATH* .
OEL
*
Figure 1. 73720 Block Diagram
Y-WRITE
LATCH
BUS CONTROL
PATH
LEXY
LEYX
(Even Path)
LEZX
16
8
8
OEYL
OEYU
8
8
M
U
X
16
OEXL
OEXU
8
16
OEXU
OEXL
OEYU
OEYL
OEZU
OEZL
Y
0:7
Y
8:15
X
0:7
X
8:15
Y-READ
LATCH
16
8
8
16
Z-READ
LATCH
8
16
T/R
OEU
OEL
Z-WRITE
LATCH
LEXZ
(Odd Path)
16
8
8
OEZL
OEZU
8
8
Z
0:7
Z
8:15
16
2527 drw 01
8
8
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