IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, D" />
參數(shù)資料
型號(hào): IDT72V831L15TFI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 16/16頁(yè)
文件大小: 0K
描述: IC SYNC FIFO 2048X9 15NS 64QFP
標(biāo)準(zhǔn)包裝: 80
系列: 72V
功能: 異步
存儲(chǔ)容量: 18.4K(2K x 9)
數(shù)據(jù)速率: 67MHz
訪問(wèn)時(shí)間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 72V831L15TFI
9
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
Figure 4. Reset Timing
NOTES:
1. Holding WENA2/
LDA (WENB2/LDB) HIGH during reset will make the pin act as a second Write Enable pin. Holding WENA2/LDA (WENB2/LDB) LOW during reset will make
the pin act as a load enable for the programmable flag offset registers.
2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if
OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
Figure 5. Write Cycle Timing
NOTE:
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for
FFA (FFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then
FFA (FFB) may not change state until the next WCLKA (WCLKB)
edge.
tDH
tENH
tSKEW1(1)
tCLK
tCLKH
tCLKL
tDS
tENS
tWFF
WCLKA (WCLKB)
(DA0 - DA8
DB0 - DB8)
WENA1
(WENB1)
WENA2 (WENB2)
(If Applicable)
FFA
(FFB)
RCLKA (RCLKB)
RENA1, RENA2
(RENB1, RENB2)
NO OPERATION
4093 drw 07
DATA IN VALID
tENS
tENH
tRS
tRSR
RSA (RSB)
RENA1, RENA2
(RENB1, RENB2)
tRSF
OEA (OEB) = 1
OEA (OEB) = 0
(2)
EFA, PAEA
(EFB, PAEB)
FFA, PAFA
(FFA, PAFA)
QA0 - QA8
(QB0 - QB8)
4093 drw 06
WENA1
(WENB1)
tRSS
tRSF
tRSR
tRSS
tRSR
tRSS
WENA2/LDA
(WENB2/LDB)
(1)
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