參數(shù)資料
型號： IDT72V73263BB
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 33/36頁
文件大?。?/td> 0K
描述： IC DGTL SW 16384X16384 208-BGA
標(biāo)準(zhǔn)包裝： 12
系列： 72V
類型： 多路復(fù)用器
電路： 8 x 1:1
電壓電源： 單電源
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 208-BGA
供應(yīng)商設(shè)備封裝： 208-PBGA（17x17）
包裝： 托盤
其它名稱： 72V73263BB
6
INDUSTRIAL TEMPERATURERANGE
IDT72V73263 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
MICROPROCESSOR INTERFACE
The IDT72V73263’s microprocessor interface looks like a standard RAM
interfacetoimproveintegrationintoasystem. Witha16-bitaddressbusand
a16-bitdatabusallmemoriescanbeaccessed. UsingtheTSImicroprocessor
interface,readsandwritesaremappedintoDataandConnectionmemories.
By allowing the internal memories to be randomly accessed, the controlling
microprocessorhasmoretimetomanageotherperipheraldevices
andcanmoreeasilyandquicklygatherinformationandsetuptheswitchpaths.
Table1showsthemappingoftheaddressesintointernalmemoryblocks. In
ordertominimizetheamountofmemorymappedspacehowever,theMemory
Select(MS1-0)bitsintheControlRegistermustbewrittentofirsttoselectbetween
theConnectionMemoryHIGH,theConnectionMemoryLOW,orDataMemory.
Effectively,theMemorySelectbitsactasaninternalmuxtoselectbetweenthe
Data Memory, Connection Memory HIGH, and Connection Memory LOW.
MEMORYMAPPING
Theaddressbusonthemicroprocessorinterfaceselectstheinternalregisters
and memoriesoftheIDT72V73263.Themostsignificantbitoftheaddressselect
between the registers and internal memories. See Table 1 for mappings.
AsexplainedintheInitializationsection,aftersystempower-up,theTDRSR
and RDRSR, should be programmed immediately to establish the desired
switchingconfiguration.
The data in the Control Register consists of the Software Reset, RX/TX
Bypass,OutputEnablePolarity,AllOutputEnable,FullBlockProgramming,
BlockProgrammingData,BeginBlockProgrammingEnable,ResetConnection
MemoryLOWinBlockProgramming,OutputStandby,andMemorySelect.
SOFTWARE RESET
The Software Reset serves the same function as the hardware reset. As
withthehardreset,theSoftwareResetmustalsobesetHIGHfor20nsbefore
bringingtheSoftwareResetLOWagainfornormaloperation. OncetheSoftware
Reset is LOW, internal registers and other memories may be read or written.
During Software Reset, the microprocessor port is still able to read from all
internalmemories.TheonlywriteoperationallowedduringaSoftwareReset
istotheSoftwareResetbitintheControlRegistertocompletetheSoftwareReset.
CONNECTION MEMORY CONTROL
If the ODE pin and the Output Standby bit are LOW, all output channels will
be in three-state. See Table 2 for detail.
IfMOD2-0oftheConnectionMemoryHIGHis1-0-0accordingly,theoutput
channel will be in Processor Mode. In this case the lower eight bits of the
Connection Memory LOW are output each frame until the MOD2-0 bits are
changed.IfMOD2-0oftheConnectionMemoryHIGHare0-0-1accordingly,
thechannelwillbeinConstantDelayModeandbits14-0areusedtoaddress
a location in Data Memory. If MOD2-0 of the Connection Memory HIGH are
0-0-0, the channel will be in Variable Delay Mode and bits 14-0 are used to
addressalocationinDataMemory.IfMOD2-0oftheConnectionMemoryHIGH
are 1-1-1, the channel will be in High-Impedance mode and that channel will
beinthree-state.
RX/TX INTERNAL BYPASS
WhentheBypassbitofcontrolregistersis1,allRXstreamswillbe“shorted”
toTX ineffectbypassingallinternalcircuitryoftheTSI. Thiseffectivelysetsthe
TSItoa1-to-1switchmodewithminimalI/Odelay. Azerocanbewrittentoallow
normaloperation.TheintentionofthismodeistominimizethedelayfromtheRX
input to the TX output making the TSI “invisible”.
INITIALIZATION OF THE IDT72V73263
Afterpowerup,thestateoftheConnectionMemoryisunknown. Assuch,the
outputsshouldbeputinHigh-ImpedancebyholdingtheODEpinLOW. While
theODEisLOW,themicroprocessorcaninitializethedevicebyusingtheBlock
Programmingfeatureandprogramtheactivepathsviathemicroprocessorbus.
Oncethedeviceisconfigured,theODEpin(orOutputStandbybitdepending
oninitialization)canbeswitchedtoenabletheTSIswitch.
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IDT72V73273BB 功能描述:IC DGTL SW 32768X32768 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復(fù)用器，解碼器 系列:72V 標(biāo)準(zhǔn)包裝:48 系列:74VHC 類型:多路復(fù)用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件
IDT72V73273BBG 功能描述:IC DGTL SW 32768X32768 208-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復(fù)用器，解碼器 系列:72V 標(biāo)準(zhǔn)包裝:48 系列:74VHC 類型:多路復(fù)用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件
IDT72V801L10PF 功能描述:IC SYNC FIFO 256X9 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V801L10PF8 功能描述:IC SYNC FIFO 256X9 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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