參數(shù)資料
型號: IDT72V70810PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 19/22頁
文件大小: 0K
描述: IC DGTL SW 1024X1024 3.3V 64TQFP
標準包裝: 750
系列: 72V
類型: 多路復用器
電路: 1 x 8:8
獨立電路: 1
電壓電源: 單電源
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V70810PF8
6
COMMERCIALTEMPERATURERANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
The data in the IMS register consists of block programming bits (BPD0-
BPD4),blockprogrammingenablebit(BPE),outputstandbybit(OSB)andstart
frameevaluationbit(SFE).Theblockprogrammingandtheblockprogramming
enablebitsallowsuserstoprogramtheentireconnectionmemory(seeMemory
BlockProgrammingsection).IftheODEpinislow,theOSBbitenables(ifhigh)
ordisables(iflow)allST-BUSoutputdrivers.IftheODEpinishigh,thecontents
of the OSB bit is ignored and all TX output drivers are enabled.
CONNECTION MEMORY CONTROL
TheCCOpinisa16.384Mb/soutput,whichcarries2,048bits.Thecontents
of the CCO bit of each connection memory location are output on the CCO pin
once every frame. The contents of the CCO bits of the connection memory are
transmitted sequentially on to the CCO pin (2 bit cells for each bit in connection
memory) and are synchronous with the data rates on the other serial streams.
The CCO bit is output one channel before the corresponding channel on the
serialstreams.
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
location controls the output drivers-enables (if high) or disables (if low). See
Table 4 for detail.
Theprocessorchannel(PC)bitoftheconnectionmemoryselectsbetween
Processor Mode and Connection Mode. If high, the contents of the connection
memoryareoutputontheTXstreams. Iflow,thestreamaddressbit(SAB)and
the channel address bit (CAB) of the connection memory defines the source
information(streamandchannel)ofthetime-slotthatwillbeswitchedtotheoutput
from data memory.
The
V/C(Variable/ConstantDelay)bitineachconnectionmemorylocation
allows the per-channel selection between variable and constant throughput
delay modes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., RX n channel m data comes from the
TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
INITIALIZATION OF THE IDT72V70810
After power up, the state of the connection memory is unknown. As such,
theoutputsshouldbeputinhighimpedancebyholdingtheODElow. Whilethe
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.
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