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參數(shù)資料
| 型號： | IDT72V70190PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 9/19頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL SW 256X256 3.3V 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | 72V |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 9:4 |
| 獨立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 72V70190PF |
2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAB2210 Rev. 1.1.2
17
FAB2210
—
Audio
Subsystem
with
Class-G
Headphone
and
3.3W
Mono
Clas
s-D
Speaker
with
Dyna
mic
Range
Compressi
on
Speaker Amplifier Noise Gate
The speaker noise gate automatically mutes the
speaker amplifier when its input amplitude is below a
predetermined noise gate threshold to reduce noise
during inactivity. (This function is more useful for speech
than music.) The amplitude is measured after the
speaker volume control, but before the speaker amplifier
block. The speaker noise gate’s threshold level is set by
the SP_NG_RAT register. The amplitude must be less
than the noise gate threshold for the hold time
determined by the NG_ATRT register.
The speed at which the volume is reduced is
determined by the attack time setting in the NG_ATRT
register. When the volume is reduced by the noise gate,
the
SP_ATT
register’s
readback
value
remains
unchanged. An internal register keeps track of the
actual volume setting.
If the speaker channel’s amplitude goes above the
speaker noise gate threshold, the speaker volume is
raised back to the SP_ATT value at a rate determined
by the release time setting in the NG_ATRT register.
To avoid unpredictable behavior, noise gate settings
should not be changed while the speaker amplifier is on.
Table 2. Speaker Volume Change Behavior
SP_SVOFF SP_ZCSOFF Behavior when SP_ATT is Changed
1
Volume changes immediately.
1
0
Wait until a zero crossing occurs in the input before changing volume. If a zero
crossing does not occur within 200 s, volume is forced to the new setting.
0
1
Volume is ramped to the new setting at a rate of 200 s per step.
0
Volume is changed by one step when a zero crossing occurs. If a zero crossing does
not occur within 200 s, a step is forced. Only the first zero crossing within 200 s
triggers a volume change; volume does not change again until the next 200 s.
Speaker Volume Ramp and Zero-Crossing
Detection
The SP_SVOFF and SP_ZCSOFF I
2C bits control the
speaker volume when SP_ATT is changed.
SP_SVOFF and SP_ZCSOFF do not slow down turn-on
or turn-off when using the SP_AMIX, SP_BMIX, or
SRST bits. Thermal, over-current, and DC offset
shutdown conditions are not slowed by SP_SVOFF and
SP_ZCSOFF.
SP_SVOFF and SP_ZCSOFF have no effect on DRC
and noise gate timing. DRC and noise gate timing have
no effect on speaker volume ramp and zero-crossing
detection. In the event of a conflict between these
systems, the lowest volume setting is chosen.
I2C Control
Writing to and reading from registers is accomplished
via the I
2C interface. The I2C protocol requires that one
device on the bus initiates and controls all read and
write operations. This device is called the “master”
device. The master device generates the SCL signal,
which is the clock signal for all other devices on the bus.
All other devices on the bus are called “slave” devices.
The FAB2210 is a slave device. Both the master and
slave devices can send and receive data on the bus.
During I
2C operations, one data bit is transmitted per
clock cycle. All I
2C operations follow a repeating nine
clock-cycle pattern that consists of eight bits (one byte)
of transmitted data followed by an acknowledge (ACK)
or not acknowledge (NACK) from the receiving device.
Note that there are no unused clock cycles during any
operation; therefore, there must be no breaks in the
stream of data and ACKs/NACKs during data transfers.
For most operations, I
2C protocol requires the SDA line
to remain stable (unmoving) whenever SCL is HIGH; i.e.
transitions on the SDA line can only occur when SCL is
LOW. The exceptions to this rule are when the master
device issues a START or STOP condition. The slave
device cannot issue a START or STOP condition.
START Condition: This condition occurs when the SDA
line transitions from HIGH to LOW while SCL is HIGH.
The master device uses this condition to indicate that a
data transfer is about to begin.
STOP Condition: This condition occurs when the SDA
line transitions from LOW to HIGH while SCL is HIGH.
The master device uses this condition to signal the end
of a data transfer.
Acknowledge and Not Acknowledge: When data is
transferred to the slave device, the slave device sends
an acknowledge (ACK) after receiving every byte of
data. The receiving device sends an ACK by pulling
SDA LOW for one clock cycle.
When the master device is reading data from the slave
device, the master sends an ACK after receiving every
byte of data. Following the last byte, a master device
sends a “not acknowledge” (NACK) instead of an ACK,
followed by a STOP condition. A NACK is indicated by
leaving SDA HIGH during the clock after the last byte.
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