參數(shù)資料
型號(hào): IDT72V51236L6BB8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 24/56頁(yè)
文件大?。?/td> 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
標(biāo)準(zhǔn)包裝: 1,000
類(lèi)型: 多隊(duì)列流量控制
安裝類(lèi)型: 表面貼裝
封裝/外殼: 256-BBGA
供應(yīng)商設(shè)備封裝: 256-BGA(17x17)
包裝: 帶卷 (TR)
其它名稱(chēng): 72V51236L6BB8
30
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Figure 6. Serial Port Connection for Serial Programming
DFM
MRS
SENI
SENO
MQ1
SI
SO
SCLK
DFM
MRS
SENI
SENO
MQ2
SI
SO
SCLK
DFM
MRS
SENI
SENO
MQn
SI
SO
SCLK
Serial Enable
Serial Input
Serial Clock
Default Mode
DFM = 0
Master Reset
Serial Loading
Complete
5937 drw11
Figure 5. Partial Reset
NOTES:
1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.
2. The queue must be selected a minimum of 2 clock cycles before the Partial Reset takes place, on both the write and read ports.
3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.
4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.
5. The
PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.
6. The
PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
WCLK
RCLK
RDADD
tAH
tAS
tQH
tQS
Qx
RADEN
r-2
r-1
r
PRS
r+2
r+1
tPRSH
tPRSS
REN
tENS
r+3
tENS
tROV
OV
tRAE
PAE
5937 drw10
WEN
WADEN
tAH
tAS
WRADD
Qx
w-2
w-1
w
w+1
w+2
tQH
tQS
tENS
w+3
tENS
FF
tWFF
PAF
tWAF
Active Bus
PAF-Qx(5)
tPAF
Active Bus
PAE-Qx(6)
tPAE
tPRSH
tPRSS
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