IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
參數(shù)資料
型號(hào): IDT72V3690L7-5BBI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 7/46頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SS 32768X36 7-5N 144BGA
標(biāo)準(zhǔn)包裝: 1
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 1.1M(32K x 36)
數(shù)據(jù)速率: 133MHz
訪問(wèn)時(shí)間: 5ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-BGA
供應(yīng)商設(shè)備封裝: 144-PBGA(13x13)
包裝: 托盤
其它名稱: 72V3690L7-5BBI
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
Figure 3. Programmable Flag Offset Programming Sequence
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
WCLK
RCLK
X
XX
X
XX
LD
0
X
1
0
WEN
0
1
0
X
1
REN
1
0
1
X
0
1
1X
SEN
1
X
0
No Operation
Write Memory
Read Memory
No Operation
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
IDT72V3640
IDT72V3650
IDT72V3660
IDT72V3670
IDT72V3680
IDT72V3690
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
20 bits for the 72V3640
22 bits for the 72V3650
24 bits for the 72V3660
26 bits for the 72V3670
28 bits for the 72V3680
30 bits for the 72V3690
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
4667 drw06
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