IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
參數(shù)資料
型號: IDT72V3690L6BB
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 25/46頁
文件大?。?/td> 0K
描述: IC FIFO SS 32768X36 6NS 144-BGA
標(biāo)準(zhǔn)包裝: 1
系列: 72V
功能: 異步,同步
存儲容量: 1.1M(32K x 36)
數(shù)據(jù)速率: 166MHz
訪問時間: 4ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-BGA
供應(yīng)商設(shè)備封裝: 144-PBGA(13x13)
包裝: 托盤
其它名稱: 72V3690L6BB
31
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
NOTES:
1. Retransmit setup is complete after
OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore,
IR will be LOW throughout the Retransmit setup procedure.
D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690.
3.
OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 12. Retransmit Timing (FWFT Mode)
tREF
tRTS
tENH
4667 drw17
tENS
Wx
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q0 - Qn
tSKEW2
12
1
tPAFS
tHF
tPAES
tREF
Wx+1
2
W2
tENH
tRTS
WEN
tENS
W1
tENS
(4)
3
4
tENH
W3
tA
W4
tA
(4)
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