IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BU" />
參數(shù)資料
型號: IDT72V3674L15PF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 26/37頁
文件大?。?/td> 0K
描述: IC FIFO 16384X36 15NS 128QFP
標(biāo)準(zhǔn)包裝: 36
系列: 72V
功能: 異步
存儲(chǔ)容量: 576K(16K x 36)
數(shù)據(jù)速率: 67MHz
訪問時(shí)間: 15ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: 72V3674L15PF
32
COMMERCIALTEMPERATURERANGE
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Figure 26. Timing for
AFB
AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
Figure 27. Timing for Mail1 Register and
MBF1
MBF1 Flag (IDT Standard and FWFT Modes)
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35
will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will
have valid data (B9-B35 will be indeterminate).
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for
AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then
AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 write (
CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT72V3654, 4,096 for the IDT72V3664, 8,192 for the IDT72V3674.
4. If Port B size is word or byte,
AFB is set LOW by the last word or byte write of the long word, respectively.
AFB
CLKB
ENA
4664 drw 28
ENB
CLKA
12
tSKEW2
tENS2
tENH
tPAF
tENS2
tENH
tPAF
[D-(Y2+1)] Words in FIFO2
(D-Y2) Words in FIFO2
(1)
4664 drw29
CLKA
ENA
A0-A35
MBA
CSA
W/RA
CLKB
MBF1
CSB
MBB
ENB
B0-B35
W/RB
W1
tENS1
tENH
tDS
tDH
tPMF
tENS2
tENH
tDIS
tEN
tMDV
tPMR
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
tENS1
tENH
tENS2
tENH
tENS2
tENH
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