IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x " />
參數(shù)資料
型號: IDT72V3672L15PF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 28/29頁
文件大?。?/td> 0K
描述: IC FIFO 16384X36 15NS 120QFP
標(biāo)準(zhǔn)包裝: 45
系列: 72V
功能: 異步,同步
存儲容量: 576K(16K x 36)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 托盤
其它名稱: 72V3672L15PF
8
COMMERCIALTEMPERATURERANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
IDT72V3652L10(1)
IDT72V3652L15
IDT72V3662L10(1)
IDT72V3662L15
IDT72V3672L10(1)
IDT72V3672L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
100
66.7
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
10
15
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
4.5
6
ns
tCLKL
Pulse Duration, CLKA and CLKB LOW
4.5
6
ns
tDS
Setup Time, A0-A35 before CLKA
↑ and B0-B35
3
4
ns
before CLKB
tENS1
Setup Time,
CSA and W/RA, before
4
4.5
ns
CLKA
↑; CSB, and W/RB before CLKB↑
tENS2
Setup Time, ENA and MBA, before
3
4.5
ns
CLKA
↑; ENB, and MBB before CLKB↑
tRSTS
Setup Time,
RST1 or RST2 LOW before CLKA
5—
ns
or CLKB
(2)
tFSS
Setup Time, FS0 and FS1 before
RST1 and RST2 HIGH
7.5
7.5
ns
tFWS
Setup Time,
FWFT before CLKA
0—
ns
tDH
Hold Time, A0-A35 after CLKA
↑and B0-B35 after CLKB↑
0.5
1
ns
tENH
Hold Time,
CSA, W/RA, ENA, and MBA after CLKA
↑;
0.5
1
ns
CSB, W/RB, ENB, and MBB after CLKB
tRSTH
Hold Time,
RST1 or RST2 LOW after CLKA
↑ or CLKB↑(2)
4—
ns
tFSH
Hold Time, FS0 and FS1 after
RST1 and RST2 HIGH
2
2
ns
tSKEW1(3)
Skew Time, between CLKA
↑ and CLKB↑ for EFA/ORA,
7.5
7.5
ns
EFB/ORB, FFA/IRA, and FFB/IRB
tSKEW2(3,4)
Skew Time, between CLKA
↑ and CLKB↑ for AEA,12
12
ns
AEB, AFA, and AFB
NOTES:
1. For 10ns speed grade: Vcc = 3.3V
± 0.15V; TA = 0° to +70°.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0
°C to +70°C; JEDEC JESD8-A compliant)
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