IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
參數(shù)資料
型號(hào)： IDT72V3670L7-5PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 5/46頁(yè)
文件大?。?/td> 0K
描述： IC FIFO SS 8192X36 7-5NS 128TQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 288K（8K x 36）
數(shù)據(jù)速率： 133MHz
訪問(wèn)時(shí)間： 5ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 帶卷 (TR)
其它名稱： 72V3670L7-5PF8
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V3640/
72V3650/72V3660/72V3670/72V3680/72V3690 have internal registers for
these offsets. There are eight default offset values selectable during Master
Reset. These offset values are shown in Table 2. Offset values can also be
programmedintotheFIFOinoneoftwoways;serialorparallelloadingmethod.
The selection of the loading method is done using the
LD (Load) pin. During
MasterReset,thestateofthe
LDinputdetermineswhetherserialorparallelflag
offsetprogrammingisenabled. AHIGHon
LDduringMasterResetselectsserial
loading of offset values. A LOW on
LD during Master Reset selects parallel
loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
For a more detailed description, see discussion that follows.
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 can
be configured during the Master Reset cycle with either synchronous or
asynchronous timing for
PAF and PAE flags by use of the PFM pin.
If synchronous
PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly,
PAEisassertedandupdatedontherisingedgeofRCLK
only and not WCLK. For detail timing diagrams, see Figure 17 for synchronous
PAF timing and Figure 18 for synchronous PAE timing.
If asynchronous
PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.
PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK.Fordetailtimingdiagrams,seeFigure
19 for asynchronous
PAFtimingandFigure20forasynchronousPAEtiming.
IDT72V3640, 72V3650
LD
FSEL1
FSEL0
Offsets n,m
LH
L
511
L
H
255
L
127
LH
H
63
HL
L
31
HH
L
15
HL
H
7
HH
H
3
LD
FSEL1
FSEL0
Program Mode
H
X
Serial(3)
L
X
Parallel(4)
IDT72V3660, 72V3670, 72V3680, 72V3690
LD
FSEL1
FSEL0
Offsets n,m
H
L
1,023
LH
L
511
L
H
255
L
127
LH
H
63
HH
L
31
HL
H
15
HH
H
7
LD
FSEL1
FSEL0
Program Mode
H
X
Serial(3)
L
X
Parallel(4)
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for
PAE.
2. m = full offset for
PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
相關(guān)PDF資料
PDF描述
MAX1070ETC+T IC ADC 10BIT 1.5MSPS 12-TQFN
MS27474E10B99PC CONN RCPT 7POS JAM NUT W/PINS
IDT72V3670L7-5BB8 IC FIFO SS 8192X36 7-5NS 144BGA
VI-264-IX-B1 CONVERTER MOD DC/DC 48V 75W
VI-264-IW-F4 CONVERTER MOD DC/DC 48V 100W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72V3670L7-5PFGI 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 8192X36 7-5NS 128TQFP
IDT72V3670L7-5PFGI8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 8192X36 7-5NS 128TQFP
IDT72V3670L7-5PFI 功能描述:IC FIFO SS 8192X36 7-5NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72V3672L10PF 功能描述:IC FIFO 16384X36 10NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72V3672L10PF8 功能描述:IC FIFO 16384X36 10NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*