![](http://datasheet.mmic.net.cn/IDT--Integrated-Device-Technology-Inc/IDT72V3674L10PF_datasheet_105068/IDT72V3674L10PF_35.png)
35
COMMERCIALTEMPERATURERANGE
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
CLKA
ENB
CLKB
RT1
4664 drw33
tRSTS
tRSTH
tREF
(2)
B0-Bn
RTM
ORB
tREF
(2)
W1
Wx
13
4
2
1
34
2
tRTMS
tRTMH
LOW
tA
NOTES:
1. CSB = LOW
2. Retransmit setup is complete after ORB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, IRA will be LOW throughout the Retransmit
setup procedure. D = 2,049, 4,097 and 8,193 for the IDT72V3654, IDT72V3664 and IDT72V3674 respectively.
Figure 31. Retransmit Timing for FIFO1 (FWFT Mode)
CLKB
ENA
CLKA
RT2
4664 drw34
tRSTS
tRSTH
tREF
(2)
A0-An
RTM
ORA
tREF
(2)
W1
Wx
tA
13
4
2
1
34
2
tRTMS
tRTMH
LOW
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after ORA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO2 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRB will be LOW throughout the Retransmit
setup procedure. D = 2,049, 4,097 and 8,193 for the IDT72V3654, IDT72V3664 and IDT72V3674 respectively.
Figure 32. Retransmit Timing for FIFO2 (FWFT Mode)