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參數(shù)資料
| 型號： | IDT72V3653L15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/30頁 |
| 文件大小： | 0K |
| 描述： | IC SYNCFIFO 2048X36 15NS 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 72V |
| 功能： | 異步，同步 |
| 存儲容量： | 72K（2K x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V3653L15PF8 |
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11
COMMERCIALTEMPERATURERANGE
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
NOTE:
1. X register holds the offset for
AE; Y register holds the offset for AF.
2. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
3. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
4. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
— PRESET VALUES
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers
withoneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbe
HIGH or LOW during a reset. For example, to load the preset value of 64 into
X and Y, FS0, FS1 and FS2 must be HIGH when
RS1 returns HIGH. For
the relevant preset value loading timing diagram, see Figure 3.
— PARALLEL LOAD FROM PORT A
To program the X and Y registers from Port A, perform a Reset with FS2
HIGH or LOW and FS0 and FS1 LOW during the LOW-to-HIGH transition of
RS1. ThestateofFS2atthispointofresetwilldeterminewhethertheparallel
programming method has Intersp
arity or Non-Interspersed Parity. Refer to Table 1 for Flag Programming
FlagOffsetsetup.Itisimportanttonotethatonceparallelprogramminghasbeen
selected during a Master Reset by holding both FS0 & FS1 LOW, these inputs
must remain LOW during all subsequent FIFO operation. They can only be
toggled HIGH when future Master Resets are performed and other program-
ming methods are desired.
Afterthisresetiscomplete,thefirsttwowritestotheFIFOdonotstoredata
in RAM. The first two write cycles load the offset registers in the order Y, X. On
thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed
timingdiagram.ForNon-InterspersedParitymodethePortAdatainputsused
bytheOffsetregistersare(A10-A0),(A11-A0),or(A12-A0)fortheIDT72V3653,
IDT72V3663, or IDT72V3673, respectively. For Interspersed Parity mode the
Port A data inputs used by the Offset registers are (A11-A9, A7-A0), (A12-A9,
A7-A0),or(A13-A9,A7-A0)fortheIDT72V3653,IDT72V3663,orIDT72V3673,
respectively. The highest numbered input is used as the most significant bit of
the binary number in each case. Valid programming values for the registers
range from 1 to 2,044 for the IDT72V3653; 1 to 4,092 for the IDT72V3663; and
1 to 8,188 for the IDT72V3673. After all the offset registers are programmed
from Port A, the FIFO begins normal operation.
INTERSPERSED PARITY
Interspersed Parity is selected during a Master Reset of the FIFO. Refer
to Table 1 for the set-up configuration of Interspersed Parity. The Interspersed
Parityfunctionallowstheusertoselectthelocationoftheparitybitsintheword
loaded into the parallel port (A0-An) during programming of the flag offset
values. If Interspersed Parity is selected then during parallel programming of
the flag offset values, the device will ignore data line A8. If Non-Interspersed
Parity is selected then data line A8 will become a valid bit. If Interspersed Parity
isselectedserialprogrammingoftheoffsetvaluesisnotpermitted,onlyparallel
programming can be done.
— SERIAL LOAD
To program the X and Y registers serially, initiate a Reset with FS2 LOW,
FS0/SDLOWandFS1/
SENHIGHduringtheLOW-to-HIGHtransitionofRS1.
After this reset is complete, the X and Y register values are loaded bit-wise
through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the
FS1/
SENinputisLOW.Thereare22-,24-or26-bitwritesneededtocomplete
the programming for the IDT72V3653, IDT72V3663 or the IDT72V3673,
respectively. ThetworegistersarewrittenintheorderY,X. Eachregistervalue
can be programmed from 1 to 2,044 (IDT72V3653), 1 to 4,092 (IDT72V3663)
or 1 to 8,188 (IDT72V3673).
Whentheoptiontoprogramtheoffsetregistersseriallyischosen,theFull/
Input Ready (
FF/IR) flag remains LOW until all register bits are written. FF/
IRissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbitisloaded
to allow normal FIFO operation.
See Figure 6, Serial Programming of the Almost-Full Flag and Almost-
Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
FIFO WRITE/READ OPERATION
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
(
CSA)andPortAWrite/Readselect(W/RA). TheA0-A35linesareintheHigh-
impedance state when either
CSA or W/RA is HIGH. The A0-A35 lines are
active outputs when both
CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and
FF/IRisHIGH(seeTable2). FIFOwritesonPortAareindependent
of any concurrent reads on Port B.
ThePortBcontrolsignalsareidenticaltothoseofPortAwiththeexception
thatthePortBWrite/Readselect(
W/RB)istheinverseofthePortAWrite/Read
select (W/
RA). Thestateof the Port B data (B0-B35) lines is controlled by the
Port B Chip Select (
CSB) and Port B Write/Read select (W/RB). The B0-B35
lines are in the high-impedance state when either
CSB is HIGH or W/RB is
LOW. The B0-B35 lines are active outputs when
CSB is LOW and W/RB is
HIGH.
Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH
transition of CLKB when
CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is
FS2
FS1/
SEN
FS0/SD
RS1
X AND Y REGlSTERS(1)
HHH
↑
64
HH
L
↑
16
HL
H
↑
8
LH
H
↑
256
LL
H
↑
1,024
LH
L
↑
Serial programming via SD
HL
L
↑
Parallel programming via Port A(2,4)
LLL
↑
IP Mode(3,4)
TABLE 1 — FLAG PROGRAMMING
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