IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING 256 x 36, " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� IDT72V3633L10PF8
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 6/28闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FIFO SYNC 512X36 10NS 128TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,000
绯诲垪锛� 72V
鍔熻兘锛� 鐣版锛屽悓姝�
瀛樺劜瀹归噺锛� 18.4K锛�512 x 36锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 100MHz
瑷晱鏅傞枔锛� 10ns
闆绘簮闆诲锛� 3 V ~ 3.6 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 128-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 128-TQFP锛�14x20锛�
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� 72V3633L10PF8
14
IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURERANGE
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For
an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In this case,
A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on A0-A8. (In this case, A9-A35 are indeterminate.)
The data in a mail register remains intact after it is read and changes
only when new data is written to the register. The Endian select feature has
no effect on mailbox data. For mail register and mail register flag timing
diagrams, see Figure 17 and 18.
BUS SIZING
The Port B bus can be configured in a 36-bit long word, 18-bit word,
or 9-bit byte format for data read from the FIFO. The levels applied to the
Port B Bus Size select (SIZE) and the Bus-Match select (BM) determine the
Port B bus size. These levels should be static throughout FIFO operation.
BothbussizeselectionsareimplementedatthecompletionofReset,bythetime
the Full/Input Ready flag is set HIGH, as shown in Figure 2.
TwodifferentmethodsforsequencingdatatransferareavailableforPort
B when the bus size selection is either byte-or word-size. They are referred
toasBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificant
bytefirst). ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW-
to-HIGH transition of
RS1selectstheendianmethodthatwillbeactiveduring
FIFO operation. BE is a don鈥檛 care input when the bus size selected for Port
Bislongword. TheendianmethodisimplementedatthecompletionofReset,
by the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.
Only 36-bit long word data is written to or read from the FIFO memory on
the IDT72V3623/72V3633/72V3643. Bus-matching operations are done after
data is read from the FIFO RAM. These bus-matching operations are not
available when transferring data via mailbox registers. Furthermore, both the
word- and byte-size bus selections limit the width of the data bus that can be used
for mail register operations. In this case, only those byte lanes belonging to the
selected word- or byte-size bus can carry mailbox data. The remaining data
outputs will be indeterminate. The remaining data inputs will be don鈥檛 care inputs.
For example, when a word-size bus is selected, then mailbox data can be
transmitted only between A0-A17 and B0-B17. When a byte-size bus is
selected, then mailbox data can be transmitted only between A0-A8 and B0-
B8. (See Figures 17 and 18).
BUS-MATCHING FIFO READS
Data is read from the FIFO RAM in 36-bit long word increments. If a long
word bus size is implemented, the entire long word immediately shifts to the FIFO
output register. If byte or word size is implemented on Port B, only the first one
or two bytes appear on the selected portion of the FIFO output register, with the
rest of the long word stored in auxiliary registers. In this case, subsequent FIFO
reads output the rest of the long word to the FIFO output register in the order
shown by Figure 2.
When reading data from FIFO in byte or word format, the unused B0-B35
outputsareindeterminate.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-24Y-IU-F2 CONVERTER MOD DC/DC 3.3V 132W
VI-24Y-IU-F1 CONVERTER MOD DC/DC 3.3V 132W
VE-BNH-IV-F3 CONVERTER MOD DC/DC 52V 150W
VE-BNH-IV-F2 CONVERTER MOD DC/DC 52V 150W
MS27656T15F18PA CONN RCPT 18POS WALL MNT W/PINS
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
IDT72V3633L15PF 鍔熻兘鎻忚堪:IC FIFO SYNC 512X36 15NS 128TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V3633L15PF8 鍔熻兘鎻忚堪:IC FIFO SYNC 512X36 15NS 128TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V3634L10PF 鍔熻兘鎻忚堪:IC FIFO 512X36X2 10NS 128QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V3634L10PF8 鍔熻兘鎻忚堪:IC FIFO 512X36X2 10NS 128QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V3634L15PF 鍔熻兘鎻忚堪:IC FIFO 512X36X2 15NS 128QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF