參數(shù)資料
型號: IDT72V3632L15PQF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/29頁
文件大?。?/td> 0K
描述: IC BIFIFO 512X36X2 15NS 132-PQFP
標(biāo)準(zhǔn)包裝: 36
系列: 72V
功能: 異步,同步
存儲容量: 36.8K(512 x 36 x 2)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 132-BQFP 緩沖式
供應(yīng)商設(shè)備封裝: 132-PQFP(24.13x24.13)
包裝: 托盤
其它名稱: 72V3632L15PQF
1
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4660/8
MAY 2013
3.3 VOLT CMOS SyncBiFIFOTM
256 x 36 x 2
512 x 36 x 2
1,024 x 36 x 2
IDT72V3622
IDT72V3632
IDT72V3642
IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEATURES:
Memory storage capacity:
IDT72V3622 – 256 x 36 x 2
IDT72V3632 – 512 x 36 x 2
IDT72V3642 – 1,024 x 36 x 2
Supports clock frequencies up to 100 MHz
Fast access times of 6.5ns
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Two independent clocked FIFOs buffering data in opposite direc-
tions
Mailbox bypass register for each FIFO
Programmable Almost-Full and Almost-Empty flags
Microprocessor Interface Control Logic
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
Available space-saving 120-pin Thin Quad Flatpack (TQFP)
Functionally compatible to the 5V operating IDT723622/723632/
723642
Industrial temperature range (–40οοοοοC to +85οοοοοC) is available
Green parts available, see ordering information
DESCRIPTION:
TheIDT72V3622/72V3632/72V3642arefunctionallycompatibleversions
of the IDT723622/723632/723642, designed to run off a 3.3V supply for
exceptionally low-power consumption. These devices are monolithic, high-
FUNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Programmable Flag
Offset Registers
Input
Register
Output
Register
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
RST1
Mail 2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
FIFO2,
Mail2
Reset
Logic
RST2
MBF1
FIFO 1
FIFO 2
10
EFB/ORB
AEB
36
FFB/IRB
AFB
B0 - B35
FFA/IRA
AFA
FS0
FS1
A0 - A35
EFA/ORA
AEA
4660 drw 01
36
Timing
Mode
FWFT
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