IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM 256 x 36 x 2, 512 x 36" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� IDT72V3622L15PF8
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 3/29闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC BIFIFO 256X36X2 15NS 120-TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 750
绯诲垪锛� 72V
鍔熻兘锛� 鐣版锛屽悓姝�
瀛樺劜(ch菙)瀹归噺锛� 18.4K锛�256 x 36 x 2锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 67MHz
瑷晱(w猫n)鏅�(sh铆)闁擄細 15ns
闆绘簮闆诲锛� 3 V ~ 3.6 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
灏佽/澶栨锛� 120-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 120-TQFP锛�14x14锛�
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� 72V3622L15PF8
11
COMMERCIAL TEMPERATURERANGE
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
FIFO WRITE/READ OPERATION
ThestateoftheportAdata(A0-A35)outputsiscontrolledbyportAChip
Select (CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are
in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35
outputs are active when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is
LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA
isHIGH,MBAisLOW,andEFA/ORAisHIGH(seeTable2).FIFOreadsand
writesonportAareindependentofanyconcurrentportBoperation.Writeand
Read cycle timing diagrams for Port A can be found in Figure 4 and 7.
TheportBcontrolsignalsareidenticaltothoseofportAwiththeexception
thattheportBWrite/Readselect(W/RB)istheinverseoftheportAWrite/Read
select(W/RA).ThestateoftheportBdata(B0-B35)outputsiscontrolledbythe
port B Chip Select (CSB) and port B Write/Read select (W/RB). The B0-B35
outputs are in the high-impedance state when either CSB is HIGH or W/RB
isLOW.TheB0-B35outputsareactivewhenCSBisLOWandW/RBisHIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is
LOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs
byaLOW-to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENB
isHIGH,MBBisLOW,andEFB/ORBisHIGH(seeTable3).FIFOreadsand
writesonportBareindependentofanyconcurrentportAoperation.Writeand
Read cycle timing diagrams for Port B can be found in Figure 5 and 6.
The setup and hold time constraints to the port Clocks for the port Chip
SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations
andarenotrelatedtohigh-impedancecontrolofthedataoutputs.Ifaportenable
isLOWduringaclockcycle,theport鈥檚ChipSelectandWrite/Readselectmay
change states during the setup and hold time window of the cycle.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,
thenextwordwrittenisautomaticallysenttotheFIFO鈥檚outputregisterbythe
LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.
WhentheOutputReadyflagisHIGH,subsequentdataisclockedtotheoutput
registersonlywhenareadisselectedusingtheport鈥檚ChipSelect,Write/Read
select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, the first word will cause
theEmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionofthe
ReadClock. Thedatawordwillnotbeautomaticallysenttotheoutputregister.
Instead, data residing in the FIFO's memory array is clocked to the output
registeronlywhenareadisselected usingtheport鈥檚ChipSelect,Write/Read
select, Enable, and Mailbox select.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop
stages.Thisisdonetoimproveflagsignalreliabilitybyreducingtheprobability
of metastable events when CLKA and CLKB operate asynchronously to one
another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA.
EFB/ORB, AEB, FFB/IRB, and AFB
are synchronized to CLKB. Tables
4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB)
These are dual purpose flags. In the FWFT mode, the Output Ready
(ORA, ORB) function is selected. When the Output Ready flag is HIGH,
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
Port Function
H
X
High-Impedance
None
L
X
Input
None
LL
H
L
鈫�
Input
FIFO2 write
LL
H
鈫�
Input
Mail2write
L
H
L
X
Output
None
LH
H
L
鈫�
Output
FIFO1 read
L
H
L
H
X
Output
None
LH
H
鈫�
Output
Mail1 read (set MBF1 HIGH)
TABLE 3 鈥� PORT B ENABLE FUNCTION TABLE
TABLE 2 鈥� PORT A ENABLE FUNCTION TABLE
CSA
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Function
H
X
High-Impedance
None
L
H
L
X
Input
None
LH
H
L
鈫�
Input
FIFO1 write
LH
H
鈫�
Input
Mail1write
L
X
Output
None
LL
H
L
鈫�
Output
FIFO2 read
L
H
X
Output
None
LL
H
鈫�
Output
Mail2 read (set MBF2 HIGH)
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