IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x " />
參數(shù)資料
型號(hào)： IDT72V3614L12PQF
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 4/32頁(yè)
文件大?。?/td> 0K
描述： IC FIFO 64X36X2 12NS 132QFP
標(biāo)準(zhǔn)包裝： 36
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 4.6K（64 x 36 x2）
數(shù)據(jù)速率： 83MHz
訪問(wèn)時(shí)間： 12ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 132-BQFP 緩沖式
供應(yīng)商設(shè)備封裝： 132-PQFP（24.13x24.13）
包裝： 托盤(pán)
其它名稱： 72V3614L12PQF
IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIALTEMPERATURERANGE
12
The order of the bytes are rearranged within the long word, but the bit order
withinthebytesremainsconstant.
BytearrangementischosenbytheportBSwapselect(SW0,SW1)inputs
onaCLKBrisingedgethatreadsanewlongwordfromFIFO1orwritesanew
long word to FIFO2. The byte order chosen on the first byte or first word of a
newlongwordreadfromFIFO1orwrittentoFIFO2ismaintaineduntiltheentire
long word is transferred, regardless of the SW0 and SW1 states during
subsequentwritesorreads.Figure4isanexampleofthebyte-orderswapping
availableforlongwords.Performingabyteswapandbussizesimultaneously
foraFIFO1readfirstrearrangesthebytesasshowninFigure4,thenoutputs
thebytesasshowninFigure2.Simultaneousbus-sizingandbyte-swapping
operations for FIFO2 writes, first loads the data according to Figure 2, then
swaps the bytes as shown in Figure 4 when the long word is loaded to FIFO2
RAM.
PARITY CHECKING
TheportAinputs(A0-A35)andportBinputs(B0-B35)eachhavefourparity
treestochecktheparityofincoming(oroutgoing)data. Aparityfailureonone
ormorebytesoftheportAdatabusisreportedbyaLOWlevelontheportParity
ErrorFlag(PEFA). AparityfailureononeormorebytesoftheportBdatainput
thatarevalidforthebus-sizeimplementationisreportedbyaLOWlevelonthe
portBParityErrorFlag(PEFB). OddorEvenparitycheckingcanbeselected,
and the Parity Error Flags can be ignored if this feature is not desired.
ParitystatusischeckedoneachinputbusaccordingtotheleveloftheOdd/
Evenparity(ODD/EVEN)selectinput. Aparityerrorononeormorevalidbytes
ofaportisreportedbyaLOWlevelonthecorrespondingportParityErrorFlag
(PEFA,PEFB)output. PortAbytesarearrangedasA0-A8,A9-A17,A18-A26,
and A27-A35. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and
B27-B35,anditsvalidbytesarethoseusedinaportBbus-sizeimplementation.
When Odd/Even parity is selected, a port Parity Error Flag (PEFA, PEFB) is
LOW if any byte on the port has an odd/even number of LOW levels applied
tothebits.
ThefourparitytreesusedtochecktheA0-A35inputsaresharedbythemail2
register when parity generation is selected for port A reads (PGA = HIGH).
WhenaportAreadfromthemail2registerwithparitygenerationisselectedwith
CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A
Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to the
A0-A35inputs. Likewise,theparitytreesusedtochecktheB0-B35inputsare
sharedbythemail1registerwhenparitygenerationisselectedforportBreads
(PGB = HIGH). WhenaportBreadfromthemail1registerwithparitygeneration
isselectedwithCSBLOW,ENB HIGH,W/RBLOW,bothSIZ0andSIZ1HIGH,
and PGB HIGH, the port B Parity Error Flag (PEFB) is held HIGH regardless
of the levels applied to the B0-B35 inputs (see Figure 24 and 25).
PARITYGENERATION
A HIGH level on the port A Parity Generate select (PGA) or port B Parity
Generateselect(PGB)enablestheIDT72V3614togenerateparitybitsforport
reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8,
A9-A17,A18-26,andA27-A35,withthemostsignificantbitofeachbyteused
as the parity bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and
B27-B35,withthemostsignificantbitofeachbyteusedastheparitybit. Awrite
to a FIFO or mail register stores the levels applied to all nine inputs of a byte
regardlessofthestateoftheParityGenerateselect(PGA,PGB)inputs.When
dataisreadfromaportwithparitygenerationselected,thelowereightbitsof
eachbyteareusedtogenerateaparitybitaccordingtothelevelontheODD/
EVENselect.Thegeneratedparitybitsaresubstitutedforthelevelsoriginally
written to the most significant bits of each byte as the word is read to the data
outputs.
ParitybitsforFIFOdataaregeneratedafterthedataisreadfromSRAMand
before the data is written to the output register. Therefore, the port A Parity
Generateselect(PGA)andOdd/Evenparityselect(ODD/EVEN)havesetup
and hold time constraints to the port A Clock (CLKA) and the port B Parity
Generateselect(PGB)andODD/EVENhavesetupandhold-timeconstraints
totheportBClock(CLKB). Thesetimingconstraintsonlyapplyforarisingclock
edge used to read a new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port
B bus (B0-B35) to check parity and the circuit used to generate parity for the
mail2 data is shared by the port A bus (A0-A35) to check parity. The shared
paritytreesofaportareusedtogenerateparitybitsforthedatainamailregister
when the port Chip Select (CSA, CSB) is LOW, Enable (ENA, ENB) is HIGH,
Write/Readselect(W/RA,W/RB)inputisLOW,the Mailregisterisselected(MBA
is HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port Parity
Generateselect(PGA,PGB)isHIGH. Generatingparityformailregisterdata
does not change the contents of the register (see Figure 26 and 27).
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