IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� IDT72V293L7-5BC
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 2/45闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FIFO 65536X18 5NS 100LBGA
妯欐簴鍖呰锛� 1
绯诲垪锛� 72V
鍔熻兘锛� 鍚屾
瀛樺劜瀹归噺锛� 1.1M锛�65K x 18锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 166MHz
瑷晱鏅傞枔锛� 5ns
闆绘簮闆诲锛� 3.15 V ~ 3.45 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 100-LBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 100-CABGA锛�11x11锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 72V293L7-5BC
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
AC ELECTRICAL CHARACTERISTICS(1)鈥� ASYNCHRONOUS TIMING
(Commercial: VCC = 3.3V 卤 0.15V, TA = 0
掳C to +70掳C;Industrial: VCC = 3.3V 卤 0.15V, TA = -40掳C to +85掳C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l
IDT72V223L6
IDT72V223L7-5
IDT72V233L6
IDT72V233L7-5
IDT72V243L6
IDT72V243L7-5
IDT72V253L6
IDT72V253L7-5
IDT72V263L6
IDT72V263L7-5
IDT72V273L6
IDT72V273L7-5
IDT72V283L6
IDT72V283L7-5
IDT72V293L6
IDT72V293L7-5
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fA(4)
Cycle Frequency (Asynchronous mode)
鈥�
100
鈥�
83
MHz
tAA(4)
Data Access Time
0.6
8
0.6
10
ns
tCYC(4)
Cycle Time
10
鈥�
12
鈥�
ns
tCYH(4)
Cycle HIGH Time
4.5
鈥�
5
鈥�
ns
tCYL(4)
Cycle LOW Time
4.5
鈥�
5
鈥�
ns
tRPE(4)
Read Pulse after
EF HIGH
8
鈥�
10
鈥�
ns
tFFA(4)
Clock to Asynchronous
FF
鈥�8
鈥�
10
ns
tEFA(4)
Clock to Asynchronous
EF
鈥�8
鈥�
10
ns
tPAFA(4)
Clock to Asynchronous Programmable Almost-Full Flag
鈥�
8
鈥�
10
ns
tPAEA(4)
Clock to Asynchronous Programmable Almost-Empty Flag
鈥�
8
鈥�
10
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Parameters apply to the BGA package only.
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鍙冩暩(sh霉)鎻忚堪
IDT72V293L7-5BCI 鍔熻兘鎻忚堪:IC FIFO 65536X18 7-5NS 100BGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:15 绯诲垪:74F 鍔熻兘:鐣版 瀛樺劜瀹归噺:256锛�64 x 4锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:- 瑷晱鏅傞枔:- 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:閫氬瓟 灏佽/澶栨:24-DIP锛�0.300"锛�7.62mm锛� 渚涙噳鍟嗚ō鍌欏皝瑁�:24-PDIP 鍖呰:绠′欢 鍏跺畠鍚嶇ū:74F433
IDT72V293L7-5PF 鍔熻兘鎻忚堪:IC FIFO SYNC II 3.3V 80-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:90 绯诲垪:74ABT 鍔熻兘:鍚屾锛岄洐绔彛 瀛樺劜瀹归噺:4.6K锛�64 x 36 x2锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:67MHz 瑷晱鏅傞枔:- 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:120-LQFP 瑁搁湶鐒婄洡 渚涙噳鍟嗚ō鍌欏皝瑁�:120-HLQFP锛�14x14锛� 鍖呰:鎵樼洡 鐢�(ch菐n)鍝佺洰閷勯爜闈�:1005 (CN2011-ZH PDF) 鍏跺畠鍚嶇ū:296-3984
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