參數(shù)資料
型號(hào): IDT72V291L20TF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/26頁
文件大?。?/td> 0K
描述: IC FIFO SS 32768X36 20NS 64QFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 72V
功能: 同步
存儲(chǔ)容量: 1.1M(32K x 36)
數(shù)據(jù)速率: 50MHz
訪問時(shí)間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 72V291L20TF8
3.3 VOLT CMOS SuperSync FIFO
65,536 x 9
131,072 x 9
IDT72V281
IDT72V291
1
FEBRUARY 2009
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DSC-4513/3
FEATURES:
Choose among the following memory organizations:
IDT72V281
65,536 x 9
IDT72V291
131,072 x 9
Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs
10ns read/write cycle time (6.5ns access time)
Fixed, low first word data latency time
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable
settings
Retransmit operation with fixed, low first word data
latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using EF
EF
EF and FF
FF
FF flags) or First Word
Fall Through timing (using
OR
OR and IR
IR
IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing
simultaneously)
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin
Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial Temperature Range (-40°C to + 85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72V281/72V291 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:
Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
The period required by the retransmit operation is now fixed and short.
Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
65,536 x 9
131,072 x 9
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK
D0-D8
LD
MRS
REN
RCLK
OE
Q0-Q8
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
4513 drw 01
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