IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM 65,536 x 9 " />
參數(shù)資料
型號(hào)： IDT72V291L15TFI8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 3/26頁(yè)
文件大?。?/td> 0K
描述： IC FIFO SS 32768X36 15NS 64QFP
標(biāo)準(zhǔn)包裝： 1,250
系列： 72V
功能： 同步
存儲(chǔ)容量： 1.1M（32K x 36）
數(shù)據(jù)速率： 67MHz
訪問(wèn)時(shí)間： 15ns
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
其它名稱(chēng)： 72V291L15TFI8
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM
65,536 x 9 and 131,072 x 9
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
which consists of reading out the memory contents, starting at the beginning
of memory.
Retransmit setup is initiated by holding
RT LOW during a rising RCLK
edge.
REN and WEN must be HIGH before bringing RT LOW. At least
one word, but no more than D - 2 words should have been written into the
FIFO between Reset (Master or Partial) and the time of Retransmit setup.
D = 65,536 for the IDT72V281 and D = 131,072 for the IDT72V291 in IDT
Standard mode.
In FWFT mode, D = 65,537 for the IDT72V281 and
D = 131,073 for the IDT72V291.
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting
EF LOW. The change in level will only be
noticeable if
EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
When
EF goes HIGH, Retransmit setup is complete and read opera-
tions may begin starting with the first location in memory. Since IDT
Standard mode is selected, every word read including the first word
following Retransmit setup requires a LOW on
REN to enable the rising
edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for
the relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting
OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
When
OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on
REN is
necessary. Reading all subsequent words requires a LOW on
REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
For either IDT Standard mode or FWFT mode, updating of the
PAE,
HF and PAF flags begin with the rising edge of RCLK that RT is setup.
PAE is synchronized to RCLK, thus on the second rising edge of RCLK
after
RT is setup, the PAE flag will be updated. HF is asynchronous, thus
the rising edge of RCLK that
RT is setup will update HF. PAF is
synchronized to WCLK, thus the second rising edge of WCLK that occurs
tSKEW after the rising edge of RCLK that
RT is setup will update PAF. RT
is synchronized to RCLK.
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IDT72V291L20PF8 功能描述:IC FIFO SS 32768X36 20NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
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