- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10167 > IDT72V285L15PF (IDT, Integrated Device Technology Inc)IC FIFO SS 65536X18 15NS 64-TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT72V285L15PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 23/25頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SS 65536X18 15NS 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | 72V |
| 功能： | 異步 |
| 存儲(chǔ)容量： | 1.1M（65K x 18） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問(wèn)時(shí)間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 72V285L15PF 800-2339 IDT72V285L15PF-ND |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)當(dāng)前第23頁(yè)第24頁(yè)第25頁(yè)
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
WhenconfiguredinIDTStandardmode,the
EFandFFoutputsaredouble
register-bufferedoutputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags,
IR,PAF,HF,PAE,andORoperateinthe
manneroutlinedinTable2.TowritedataintototheFIFO,
WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitions of WCLK. After the first write is performed, the Output Ready (
OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO.
PAEwill
goHIGHaftern + 2wordshavebeenloadedintotheFIFO,wherenistheempty
offsetvalue.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the
HFwouldtoggletoLOWoncethe16,386th
word for the IDT72V275 and 32,770th word for the IDT72V285, respectively
was written into the FIFO. Continuing to write data into the FIFO will cause the
PAFtogoLOW.Again,ifnoreadsareperformed, thePAFwillgoLOWafter
(32,769-m)writesfortheIDT72V275 and(65,537-m)writesfortheIDT72V285,
where m is the full offset value. The default setting for this value is stated in the
footnote of Table 2.
WhentheFIFOisfull,theInputReady(
IR)flagwillgoHIGH,inhibitingfurther
write operations. If no reads are performed after a reset,
IRwillgoHIGHafter
D writes to the FIFO. D = 32,769 writes for the IDT72V275 and 65,537 writes
for the IDT72V285, respectively. Note that the additional word in FWFT mode
is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the
IR flag to go LOW.
Subsequent read operations will cause the
PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without write
operations,the
PAEwillgoLOWwhentherearen+1wordsintheFIFO,where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO,
ORwillgo
HIGH inhibiting further read operations.
REN is ignored when the FIFO is
empty.
When configured in FWFT mode, the
OR flag output is triple register-
buffered, and the
IRflagoutputisdoubleregister-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10 and
12.
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V275/
72V285hasinternalregistersfortheseoffsets.Defaultsettingsarestatedinthe
footnotesofTable1andTable2.OffsetvaluescanbeprogrammedintotheFIFO
inoneoftwoways;serialorparallelloadingmethod.Theselectionoftheloading
method is done using the
LD(Load)pin.DuringMasterReset,thestateofthe
LD input determines whether serial or parallel flag offset programming is
enabled. A HIGH on
LD during Master Reset selects serial loading of offset
values and in addition, sets a default
PAE offset value of 3FFH (a threshold
1,023wordsfromtheemptyboundary),andadefault
PAFoffsetvalueof3FFH
(a threshold 1,023 words from the full boundary). A LOW on
LDduringMaster
Resetselectsparallelloadingofoffsetvalues,andinaddition,setsadefault
PAE
offset value of 07FH (a threshold 127 words from the empty boundary), and
a default
PAF offset value of 07FH (a threshold 127 words from the full
boundary). See Figure 3, Offset Register Location and Default Values.
In addition to loading offset values into the FIFO, it also possible to read the
current offset values. It is only possible to read offset values via parallel read.
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V275/72V285 support two different timing modes of operation:
IDT Standard mode or First Word Fall Through (FWFT) mode. The selection
of which mode will operate is determined during Master Reset, by the state of
the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (
EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(
FF)toindicatewhetherornottheFIFOhasanyfreespaceforwriting. InIDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (
REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR)toindicatewhetherornotthere
is valid data at the data outputs (Qn). It also uses Input Ready (
IR)toindicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,
REN=LOWisnotnecessary. Subsequentwordsmustbeaccessed
using the Read Enable (
REN) and RCLK.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags,
FF,PAF,HF,PAE,andEFoperateinthe
manneroutlinedinTable1.TowritedataintototheFIFO,WriteEnable(
WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (
EF)willgoHIGH.Subsequentwriteswillcontinue
to fill up the FIFO. The Programmable Almost-Empty flag (
PAE)willgoHIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for this value is stated in the footnote of Table 1. This
parameter is also user programmable. See section on Programmable Flag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(
HF)wouldtoggletoLOWonce
the 16,385th word for IDT72V275 and 32,769th word for IDT72V285
respectively was written into the FIFO. Continuing to write data into the FIFO
will cause the Programmable Almost-Full flag (
PAF) to go LOW. Again, if no
reads are performed, the
PAF will go LOW after (32,768-m) writes for the
IDT72V275 and (65,536-m) writes for the IDT72V285. The offset “m” is the full
offsetvalue.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
When the FIFO is full, the Full Flag (
FF)willgoLOW,inhibitingfurtherwrite
operations. Ifnoreadsareperformedafterareset,
FFwillgoLOWafterDwrites
to the FIFO. D = 32,768 writes for the IDT72V275 and 65,536 for the
IDT72V285, respectively.
If the FIFO is full, the first read operation will cause
FF to go HIGH.
Subsequent read operations will cause
PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without write
operations,
PAE will go LOW when there are n words in the FIFO, where n
is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, the
EFwill
go LOW inhibiting further read operations.
REN is ignored when the FIFO is
empty.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC1605-1CG#TR | IC ADC 16BIT 5V SAMPLING 28SSOP |
| 97-3106A-24-5P | CONN PLUG 16POS STRAIGHT W/PIN |
| VI-B7L-MY | CONVERTER MOD DC/DC 28V 50W |
| IDT72285L20PF | IC FIFO 65536X18 LP 20NS 64-TQFP |
| MS3101R24-11S | CONN RCPT 9POS PANEL MNT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72V285L15PF8 | 功能描述:IC FIFO SS 65536X18 15NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V285L15PFI | 功能描述:IC FIFO SS 65536X18 15NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V285L15PFI8 | 功能描述:IC FIFO SS 65536X18 15NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V285L15TF | 功能描述:IC FIFO SS 65536X18 15NS 64STQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V285L15TF8 | 功能描述:IC FIFO SS 65536X18 15NS 64STQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。