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參數(shù)資料
| 型號： | IDT72V281L10TF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 26/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 32768X18 10NS 64QFP |
| 標(biāo)準(zhǔn)包裝： | 80 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 589K（32K x 18） |
| 數(shù)據(jù)速率： | 100MHz |
| 訪問時間： | 10ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 72V281L10TF |
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9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM
65,536 x 9 and 131,072 x 9
Figure 4. Programmable Flag Offset Programming Sequence
Figure 3. Offset Register Location and Default Values
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
WCLK
RCLK
X
XX
X
XX
4513 drw 07
LD
0
X
1
0
WEN
0
1
0
X
1
REN
1
0
1
X
0
1
X
SEN
1
X
0
Parallel write to registers:
Empty Offset (LSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
Empty Offset (MSB)
Serial shift into registers:
32 bits for the 72V281
Full Offset (LSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
Serial shift into registers:
Empty Offset (Mid-Byte)
Full Offset (Mid-Byte)
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Parallel write to registers:
Empty Offset (LSB)
Full Offset (MSB)
Full Offset (Mid-Byte)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
34 bits for the 72V291
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
72V281
72V291
EMPTY OFFSET (LSB) REGISTER
87
0
72V281 (65,536 x 9BIT)
FULL OFFSET (LSB) REGISTER
8
7
0
FULL OFFSET (MSB) REGISTER
87
0
DEFAULT VALUE
7FH if
LD is LOW at Master Reset
FFH if
LD is HIGH at Master Reset
DEFAULT VALUE
00H if
LD is LOW at Master Reset
03H if
LD is HIGH at Master Reset
DEFAULT VALUE
7FH if
LD is LOW at Master Reset
FFH if
LD is HIGH at Master Reset
EMPTY OFFSET (MSB) REGISTER
87
0
DEFAULT VALUE
00H if
LD is LOW at Master Reset
03H if
LD is HIGH at Master Reset
EMPTY OFFSET (LSB) REGISTER
87
0
72V291 (131,072 x 9BIT)
FULL OFFSET (LSB) REGISTER
87
0
FULL OFFSET (MID-BYTE) REGISTER
8
7
0
DEFAULT VALUE
7FH if
LD is LOW at Master Reset
FFH if
LD is HIGH at Master Reset
DEFAULT VALUE
7FH if
LD is LOW at Master Reset
FFH if
LD is HIGH at Master Reset
DEFAULT VALUE
00H if
LD is LOW at Master Reset
03H if
LD is HIGH at Master Reset
EMPTY OFFSET (MID-BYTE) REGISTER
87
0
DEFAULT VALUE
00H if
LD is LOW at Master Reset
03H if
LD is HIGH at Master Reset
81
0
0H
80
1
DEFAULT
0H
DEFAULT
EMPTY OFFSET
(MSB) REGISTER
FULL OFFSET
(MSB) REGISTER
4513 drw 06
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| IDT72V281L10TF8 | 功能描述:IC FIFO 32768X18 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V281L10TFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 10NS 64QFP |
| IDT72V281L10TFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 32768X18 10NS 64QFP |
| IDT72V281L15PF | 功能描述:IC FIFO 32768X18 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V281L15PF8 | 功能描述:IC FIFO 32768X18 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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