IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� IDT72V263L6PF8
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 26/45闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FIFO 8192X18 6NS 80QFP
妯欐簴鍖呰锛� 750
绯诲垪锛� 72V
鍔熻兘锛� 鐣版锛屽悓姝�
瀛樺劜瀹归噺锛� 144K锛�8K x 18锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 166MHz
瑷晱鏅傞枔锛� 4ns
闆绘簮闆诲锛� 3.15 V ~ 3.45 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 80-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 80-TQFP锛�14x14锛�
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� 72V263L6PF8
32
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
SEN
SI
4666 drw18
tENH
tENS
LD
tDS
BIT 0
EMPTY OFFSET
BIT X(1)
BIT 0
FULL OFFSET
tENH
tLDH
tDH
tLDH
BIT X(1)
tLDS
NOTES:
1. x9 to x9 mode: X = 9 for the IDT72V223, X = 10 for the IDT72V233, X = 11 for the IDT72V243, X = 12 for the IDT72V253, X = 13 for the IDT72V263, X = 14 for the IDT72V273,
X = 15 for the IDT72V283 and X = 16 for the IDT72V293.
2. All other modes: X = 8 for the IDT72V223, X = 9 for the IDT72V233, X = 10 for the IDT72V243, X = 11 for the IDT72V253, X = 12 for the IDT72V263, X = 13 for the IDT72V273,
X = 14 for the IDT72V283 and X = 15 for the IDT72V293.
tA
tRTS
tENH
4666 drw17
tENS
Wx
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q0 - Qn
tSKEW2
12
1
tPAFS
tHF
tPAES
Wx+1
2
W3
WEN
tENS
W2
(3)
4
5
tENH
W4
W5
(3)
3
W1
tA
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (
OR), will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore,
IR will be LOW throughout the Retransmit setup procedure.
If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263,
16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385
for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293.
3.
OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during
MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
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IDT72V263L6PFG 鍔熻兘鎻忚堪:IC FIFO 8192X18 6NS 80QFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V263L7-5BC 鍔熻兘鎻忚堪:IC FIFO 8192X18 7-5NS 100BGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V263L7-5BCGI 鍒堕€犲晢:Integrated Device Technology Inc 鍔熻兘鎻忚堪:IC FIFO 8192X18 5NS 100LBGA
IDT72V263L7-5BCGI8 鍒堕€犲晢:Integrated Device Technology Inc 鍔熻兘鎻忚堪:IC FIFO 3.3V SUPERSYNC II 100LBG
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