參數(shù)資料
型號(hào)： IDT72V261LA15PFI8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 26/27頁(yè)
文件大?。?/td> 0K
描述： IC FIFO SS 8192X18 15NS 64QFP
標(biāo)準(zhǔn)包裝： 750
系列： 72V
功能： 同步
存儲(chǔ)容量： 144K（8K x 18）
數(shù)據(jù)速率： 67MHz
訪問(wèn)時(shí)間： 15ns
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 72V261LA15PFI8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO 16,384 x 9 and 32,768 x 9
8
JANUARY 30, 2009
IDT72V271LA
FF PAF HF PAE EF
00
L
H
L
H
1 to n+1 (1)
LH
H
L
(n + 2) to 8,193
(n + 2) to 16,385
L
H
L
8,194 to (16,385-(m+1))(2)
16,386 to (32,769-(m+1)) (2)
LH
L
H
L
(16,385-m) to 16,384
(32,769-m) (2) to 32,768
L
H
L
16,385
32,769
H
L
H
L
IDT72V261LA
FF PAF HF PAE EF
00
H
L
1 to n (1)
HH
H
L
H
(n + 1) to 8,192
(n + 1) to 16,384
H
8,193 to (16,384-(m+1))
16,385 to (32,768-(m+1))
HH
L
H
(16,384-m)(2) to 16,383
(32,768-m) (2) to 32,767
H
L
H
16,384
32,768
L
H
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The
IDT72V261LA/72V271LA has internal registers for these offsets. De-
fault settings are stated in the footnotes of Table 1 and Table 2. Offset
values can be programmed into the FIFO in one of two ways; serial or
parallel loading method. The selection of the loading method is done
using the
LD (Load) pin. During Master Reset, the state of the LD input
determines whether serial or parallel flag offset programming is en-
abled. A HIGH on
LD during Master Reset selects serial loading of
offset values and in addition, sets a default
PAE offset value of 3FFH (a
threshold 1,023 words from the empty boundary), and a default
PAF
offset value of 3FFH (a threshold 1,023 words from the full boundary).
A LOW on
LD during Master Reset selects parallel loading of offset
values, and in addition, sets a default
PAE offset value of 07FH (a
threshold 127 words from the empty boundary), and a default
PAF
offset value of 07FH (a threshold 127 words from the full boundary).
See Figure 3, Offset Register Location and Default Values.
In addition to loading offset values into the FIFO, it also possible to read
the current offset values. It is only possible to read offset values via parallel
read.
Figure 4, Programmable Flag Offset Programming Sequence, summa-
rizes the control pins and sequence for both serial and parallel program-
ming modes. For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming
has been selected.
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
TABLE 2 — STATUS FLAGS FOR FWFT MODE
Number of
Words in
FIFO
Number of
Words in
FIFO (1)
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IDT72V261LA15TF8 功能描述:IC FIFO SS 8192X18 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱:72271LA10PF
IDT72V261LA15TFI 功能描述:IC FIFO SS 8192X18 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱:72271LA10PF
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