IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� IDT72V243L7-5BCI
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 8/45闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FIFO 2048X18 7-5NS 100BGA
妯欐簴鍖呰锛� 1
绯诲垪锛� 72V
鍔熻兘锛� 鐣版锛屽悓姝�
瀛樺劜瀹归噺锛� 36.8K锛�2K x 18锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 133MHz
瑷晱鏅傞枔锛� 5ns
闆绘簮闆诲锛� 3.15 V ~ 3.45 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 100-LBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 100-CABGA锛�11x11锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 72V243L7-5BCI
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
WCLK
RCLK
X
XX
X
XX
LD
0
X
1
0
WEN
0
1
0
X
1
REN
1
0
1
X
0
1
1X
SEN
1
X
0
No Operation
Write Memory
Read Memory
No Operation
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
Ending with Full Offset (MSB)
IDT72V223, IDT72V233
IDT72V243, IDT72V253
IDT72V263, IDT72V273
IDT72V283, IDT72V293
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
20 bits for the IDT72V223
22 bits for the IDT72V233
24 bits for the IDT72V243
26 bits for the IDT72V253
28 bits for the IDT72V263
30 bits for the IDT72V273
32 bits for the IDT72V283
34 bits for the IDT72V293
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Serial shift into registers:
Ending with Full Offset (MSB)
18 bits for the IDT72V223
20 bits for the IDT72V233
22 bits for the IDT72V243
24 bits for the IDT72V253
26 bits for the IDT72V263
28 bits for the IDT72V273
30 bits for the IDT72V283
32 bits for the IDT72V293
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
x9 to x9 Mode
All Other Modes
4666 drw06a
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
鐩搁棞PDF璩囨枡
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