IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 1" />
參數(shù)資料
型號(hào): IDT72V235L15PFI8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 13/25頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SYNC 2048X18 15NS 64TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 同步
存儲(chǔ)容量: 36.8K(2K x 18)
數(shù)據(jù)速率: 67MHz
訪問時(shí)間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V235L15PFI8
20
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARCH 2013
Figure 25. Write Cycle Timing with Double Register-Buffered FF
FF
FF (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the FF deassertion may be delayed an extra WCLK cycle.
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
WCLK
D0 - D17
WEN
FF
RCLK
REN
tDS
tWFF
DATA IN VALID
NO OPERATION
(1)
tSKEW1
4294 drw 25
tENS
tDH
tENH
1
2
tCLKH
tCLKL
tCLK
D0 - D17
WEN
RCLK
FF
REN
tENH
Q0 - Q17
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
LOW
OE
tSKEW1
DATA WRITE
4294 drw 24
WCLK
NO WRITE
1
2
1
2
tDS
NO WRITE
tWFF
tA
tENS
tSKEW1
tDS
tA
Wd
(1)
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