IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO" />
參數(shù)資料
型號(hào)： IDT72V2103L7-5BC
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 44/46頁(yè)
文件大小： 0K
描述： IC FIFO SUPERSYNCII 7-5NS 100BGA
標(biāo)準(zhǔn)包裝： 1
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 2.3K（131 x 18）
數(shù)據(jù)速率： 133MHz
訪問(wèn)時(shí)間： 5ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LBGA
供應(yīng)商設(shè)備封裝： 100-CABGA（11x11）
包裝： 托盤(pán)
其它名稱： 72V2103L7-5BC
7
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
Symbol
Name
I/O
Description
PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES)
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 41-45 and Figures 31-33.
PIN DESCRIPTION (BGA PACKAGE ONLY)
Symbol
Name
I/O
Description
ASYR(1)
Asynchronous
I
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port
will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
ASYW(1)
Asynchronous
I
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
WritePort
will select Asynchronous operation.
TCK(2)
JTAG Clock
I
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the
device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change
on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI(2)
JTAG Test Data
I
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Input
seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister.
An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO(2)
JTAG Test Data
O
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Output
seriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypass
Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS(2)
JTAG Mode
I
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthedevicethrough
its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST(2)
JTAG Reset
I
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller will automatically reset upon
power-up. If the JTAG function is not used then this signal should to be tied to GND.
RM(1)
RetransmitTiming
I
During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
Mode
normal latency mode.
RT
Retransmit
I
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable
flag settings.
RT is useful to reread data from the first physical location of the FIFO.
SEN
Serial Enable
I
SENenablesserialloadingofprogrammableflagoffsets.
WCLK/
WriteClock/
I
If Synchronous operation of the write port has been selected, when enabled by
WEN, the rising edge of WCLK
WR
WriteStrobe
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the
FIFO on a rising edge in an Asynchronous manner, (
WENshouldbetiedtoitsactivestate).Asynchronousoperation
of the WCLK/WR input is only available in the BGA package.
WEN
WriteEnable
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
VCC
+3.3V Supply
I
These are VCC supply inputs and must be connected to the 3.3V supply rail.
NOTE:
1. Inputs should not change state after Master Reset.
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