IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
參數(shù)資料
型號(hào): IDT72V2103L6PF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 20/46頁(yè)
文件大小: 0K
描述: IC FIFO SUPERSYNCII 6NS 80-TQFP
標(biāo)準(zhǔn)包裝: 45
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 2.3K(131 x 18)
數(shù)據(jù)速率: 166MHz
訪問(wèn)時(shí)間: 4ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-TQFP(14x14)
包裝: 托盤(pán)
其它名稱: 72V2103L6PF
27
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
Figure
9.
Write
Timing
and
First
Data
Word
Latency
Timing
(First
Word
Fall
Through
Mode)
NOTES:
1.
tSKEW1
is
the
minimum
time
between
a
rising
WCLK
edge
and
a
rising
RCLK
edge
to
guarantee
that
OR
will
go
LOW
after
two
RCLK
cycles
plus
t
REF
.If
the
time
between
the
rising
edge
of
WCLK
and
the
rising
edge
of
RCLK
is
less
than
tSKEW1
,then
OR
assertion
may
be
delayed
one
extra
RCLK
cycle.
2.
tSKEW2
is
the
minimum
time
between
a
rising
WCLK
edge
and
a
rising
RCLK
edge
to
guarantee
that
PAE
will
go
HIGH
after
one
RCLK
cycle
plus
t
PAES
.If
the
time
between
the
rising
edge
of
WCLK
and
the
rising
edge
of
RCLK
is
less
than
tSKEW2
,then
the
PAE
deassertion
may
be
delayed
one
extra
RCLK
cycle.
3.
LD
=
HIGH,
OE
=
LOW
4.
n=
PAE
offset,
m
=
PAF
offset
and
D
=
maximum
FIFO
depth.
5.
If
x18
Input
or
x18
Output
bus
Width
is
selected,
D
=
131,073
for
the
IDT72V2103
and
262,145
for
the
IDT72V2113.
Ifboth
x9
Input
and
x9
Output
bus
Widths
are
selected,
D
=
262,145
for
the
IDT72V2103
and
524,289
for
the
IDT72V2113.
6.
First
data
word
latency:
t
SKEW1
+
2*T
RCLK
+
t
REF
.
W
1
W
2
W
4
W
[n
+2]
W
[D-m-1]
W
[D-m-2]
W
[D-1]
W
D
W
[n+3]
W
[n+4]
W
[D-m]
W
[D-m+1]
WCLK
WEN
D
0
-
D
17
RCLK
tDH
tDS
tENS
tSKEW1
(1)
REN
Q
0
-Q
17
PAF
HF
PAE
IR
tDS
tSKEW2
tA
tREF
OR
tPAES
tHF
tPAFS
tWFF
W
[D-m+2]
W
1
tENH
6119
drw12
DATA
IN
OUTPUT
REGISTER
(2)
W
3
1
2
3
1
D-1
]
[
W
D-1
]
[
W
D-1
]
[
W
1
2
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