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參數(shù)資料
| 型號： | IDT72T6360L7-5BBI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 44/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLOW-CTRL 48BIT 7-5NS 324-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 連續(xù)流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA |
| 供應(yīng)商設(shè)備封裝： | 324-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T6360L7-5BBI |
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49
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FEBRUARY 10, 2009
GND
Transfer Clock
FWFT
WCLK
WEN
FF
Dn
IDEM
SFC
#1
RCLK
OR
REN
Qn
WCLK
WEN
IR
Dn
IDEM
SFC
#2
RCLK
EF
REN
Qn
VCC
Write Clock
Write Enable
Full Flag
Data Inputs
Read Clock
Empty Flag
Read Enable
Data Outputs
6357 drw48
VCC
Transfer Clock
FWFT
WCLK
WEN
IR
Dn
IDEM
SFC
#1
RCLK
OR
REN
Qn
WCLK
WEN
IR
Dn
IDEM
SFC
#2
RCLK
OR
REN
Qn
GND
Write Clock
Write Enable
Input Ready Flag
Data Inputs
Read Clock
Output Ready Flag
Read Enable
Data Outputs
6357 drw49
Figure 34. Depth Expansion Configuration in IDT Standard Mode
Figure 35. Depth Expansion Configuration in FWFT Mode
DEPTH EXPANSION CONFIGURATION
The sequential flow-control (SFC) device can be connected with multiple
SFCs in depth expansion to provide additional storage density that’s greater
than 1Gb. In depth expansion mode, two or mode devices are connected
throughacommontransferinterface,asshowninFigure34. Thetransferclock
can be a separate free-running clock or driven from the same system write or
read clock.
In depth expansion configuration, the first word written to an empty configu-
ration will pass from the first SFC to the next until it appears on the second (or
last) SFC in the chain. If no reads are performed, data will begin accumulating
in the second SFC until it is full. Once the second SFC is full it will disable the
REN to the first SFC. At this point data will begin accumulating in the first SFC.
Oncebothdevicesarefull,theentireconfigurationisfullandthefullflagindicator
will go LOW.
For an empty configuration, the amount of time it takes for the empty flag of
the second (or last) SFC in the chain to go LOW (i.e. valid data available to be
read out of the device) after a word has been written into the first FIFO is the
sum of the delays for each individual SFC:
(N - 1) x (4 x transfer clock) + 3 x RCLK
Where N is the number of SFCs in the chain and RCLK is the RCLK period
in ns. This latency is only noticeable for the first word written to an empty
configuration. There will be no delay evident for subsequent words written into
the chain.
In the full configuration, the amount of time it takes for the FF of the first SFC
to go from LOW to HIGH after reading one word from the chain is the sum of the
delays for each individual SFC:
(N - 1) x (3 x transfer clock) + 2 x WCLK
DepthexpansionisavailableinbothIDTStandardmodeandFirstWordFall
Through (FWFT) mode. If IDT Standard mode is selected, the IDEM signal
needstobeHIGH. IfFWFTmodeisselected,theIDEMsignalneedstobeLOW.
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