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| 型號： | IDT72T6360L6BBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 19/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLOW-CTRL 36BIT 6NS 324-BGA |
| 標準包裝： | 1 |
| 類型： | 連續(xù)流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA |
| 供應商設備封裝： | 324-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T6360L6BBG |
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26
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FEBRUARY 10, 2009
EMPTY FLAG (
EF/OR)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (
EF)
function is selected. When the SFC is empty,
EFwillgoLOW,inhibitingfurther
read operations. When
EF is HIGH, the SFC is not empty. Figure 10, Empty
Boundary – IDT Standard Mode for the relevant timing information.
In FWFT mode, the Output Ready (
OR)functionisselected.ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptySFCappearsvalidonthe
outputs.
ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshiftsthe
last word from the SFC to the outputs.
OR goes HIGH only with a true read
(RCLK with
REN = LOW). The previous data stays at the outputs, indicating
the last word was read. Further data reads are inhibited until
OR goes LOW
again. See Figure 11, Empty Boundary (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF is a double register-buffered output. In FWFT
mode,
OR isatripleregister-bufferedoutput.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF)
The Programmable Almost-Full flag (
PAF) will go LOW when the SFC
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS),PAF will go LOW after (D - m) words are written
to the SFC. See Figure 22, Synchronous
PAFFlag-IDTStandardModeand
FWFT Mode, for the relevant timing information.
If asynchronous
PAFconfigurationisselected,thePAFisassertedLOWon
the LOW-to-HIGH transition of the Write Clock (WCLK).
PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). Ifsynchronous
PAF
configuration is selected, the
PAF is updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE)
The Programmable Almost-Empty flag (
PAE) will go LOW when the SFC
reaches the almost-empty condition. In IDT Standard mode,
PAEwillgoLOW
whentherearenwordsorlessintheSFC.Theoffset“n”istheemptyoffsetvalue.
The default setting for this value is in Table 10, Device Configuration.
In FWFT mode, the
PAE will go LOW when there are n+1 words or less in
the SFC. See Figure 21, Synchronous
PAE Flag - IDT Standard Mode and
FWFT Mode, for the relevant timing information.
Ifasynchronous
PAEconfigurationisselected,thePAEisassertedLOWon
the LOW-to-HIGH transition of the Read Clock (RCLK).
PAEisresettoHIGH
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). Ifsynchronous
PAE
configuration is selected, the
PAE is updated on the rising edge of RCLK.
DATA OUTPUTS (Q0-Q35)
(Q0-Q35) are data outputs for 36-bit wide data, (Q0 - Q17) are data outputs
for 18-bit wide data or (Q0-Q8) are data outputs for 9-bit wide data.
MEMORY CLOCK OUTPUT (CK)
These signals are to be connected to the external DDR SDRAM's clock
input.
MEMORY CLOCK OUTPUT INVERTED (
CK)
ThesesignalsaretobeconnectedtotheexternalDDRSDRAM'sdifferential
clockinput.
MEMORY BANK ADDRESS INPUT BIT (BA[1:0])
These signals are to be connected to the external DDR SDRAM's bank
address input bits.
MEMORY COLUMN ADDRESS STROBE (
CAS)
These signals are to be connected to the external DDR SDRAM's column
address strobe input.
MEMORY ADDRESS BUS (A[12:0])
These signals are to be connected to the external DDR SDRAM's address
bus.
MEMORY WRITE ENABLE (
WE)
These signals are to be connected to the external DDR SDRAM's write
enable.
MEMORY ROW ADDRESS STROBE (
RAS)
These signals are to be connected to the external DDR SDRAM's row
address strobe input.
BI-DIRECTIONAL I/O
MEMORY DATA INPUTS/OUTPUTS DQ[63:0]
These signals are to be connected to the external DDR SDRAM's data input
bus.
MEMORY DATA STROBE OUTPUT DQS[7:0]
ThesesignalsaretobeconnectedtotheexternalDDRSDRAM'sdatastrobe
inputs.
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