IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO

      參數(shù)資料
      型號(hào): IDT72T1875L4-4BB
      廠商: IDT, Integrated Device Technology Inc
      文件頁(yè)數(shù): 13/55頁(yè)
      文件大?。?/td> 0K
      描述: IC FIFO 16384X18 2.5V 4NS 144BGA
      標(biāo)準(zhǔn)包裝: 1
      系列: 72T
      功能: 異步,雙端口
      存儲(chǔ)容量: 288K(16K x 18)
      數(shù)據(jù)速率: 10MHz
      訪問時(shí)間: 3.4ns
      電源電壓: 2.375 V ~ 2.625 V
      工作溫度: 0°C ~ 70°C
      安裝類型: 表面貼裝
      封裝/外殼: 144-BGA
      供應(yīng)商設(shè)備封裝: 144-PBGA(13x13)
      包裝: 托盤
      其它名稱: 72T1875L4-4BB
      20
      COMMERCIALANDINDUSTRIAL
      TEMPERATURERANGES
      IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
      8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
      FEBRUARY 10, 2009
      Figure 3. Programmable Flag Offset Programming Sequence (Continued)
      x9 to x9 Mode
      All Other Modes
      # of Bits Used:
      12 bits for the IDT72T1845
      13 bits for the IDT72T1855
      14 bits for the IDT72T1865
      15 bits for the IDT72T1875
      16 bits for the IDT72T1885
      17 bits for the IDT72T1895
      18 bits for the IDT72T18105
      19 bits for the IDT72T18115
      20 bits for the IDT72T18125
      Note: All unused bits of the
      LSB & MSB are don’t care
      # of Bits Used:
      Note: All unused bits of the
      LSB & MSB are don’t care
      11 bits for the IDT72T1845
      12 bits for the IDT72T1855
      13 bits for the IDT72T1865
      14 bits for the IDT72T1875
      15 bits for the IDT72T1885
      16 bits for the IDT72T1895
      17 bits for the IDT72T18105
      18 bits for the IDT72T18115
      19 bits for the IDT72T18125
      D/Q8
      D/Q0
      EMPTY OFFSET REGISTER
      1
      2
      3
      4
      5
      6
      7
      8
      1st Parallel Offset Write/Read Cycle
      2nd Parallel Offset Write/Read Cycle
      3rd Parallel Offset Write/Read Cycle
      4th Parallel Offset Write/Read Cycle
      D/Q8
      D/Q0
      EMPTY OFFSET REGISTER
      9
      10
      11
      12
      13
      14
      15
      16
      D/Q8
      D/Q0
      FULL OFFSET REGISTER
      1
      2
      3
      4
      5
      6
      7
      8
      D/Q8
      D/Q0
      EMPTY OFFSET REGISTER
      17
      5th Parallel Offset Write/Read Cycle
      D/Q8
      D/Q0
      FULL OFFSET REGISTER
      9
      10
      11
      12
      13
      14
      15
      16
      6th Parallel Offset Write/Read Cycle
      D/Q8
      D/Q0
      17
      FULL OFFSET REGISTER
      IDT72T1895/72T18105/72T18115/72T18125(1) x9 Bus Width
      D/Q8
      D/Q0
      EMPTY OFFSET REGISTER
      1
      2
      3
      4
      5
      6
      7
      8
      1st Parallel Offset Write/Read Cycle
      2nd Parallel Offset Write/Read Cycle
      3rd Parallel Offset Write/Read Cycle
      D/Q8
      D/Q0
      EMPTY OFFSET REGISTER
      9
      10
      11
      12
      13
      14
      15
      16
      D/Q8
      D/Q0
      FULL OFFSET REGISTER
      1
      2
      3
      4
      5
      6
      7
      8
      4th Parallel Offset Write/Read Cycle
      D/Q8
      D/Q0
      FULL OFFSET REGISTER
      9
      10
      11
      12
      13
      14
      15
      16
      IDT72T1845/72T1855/72T1865/72T1875/
      72T1885/72T1895(1) x9 Bus Width
      D/Q17
      D/Q0
      D/Q16
      EMPTY OFFSET REGISTER
      Data Inputs/Outputs
      # of Bits Used
      1
      2
      3
      4
      5
      6
      7
      8
      9
      10
      11
      12
      13
      14
      15
      16
      1st Parallel Offset Write/Read Cycle
      Data Inputs/Outputs
      2nd Parallel Offset Write/Read Cycle
      1
      2
      3
      4
      5
      6
      7
      8
      10
      11
      12
      13
      14
      15
      9
      FULL OFFSET REGISTER
      1
      2
      3
      4
      5
      6
      7
      8
      9
      10
      11
      12
      13
      14
      15
      16
      1
      2
      3
      4
      5
      6
      7
      8
      10
      11
      12
      13
      14
      15
      9
      Non-Interspersed
      Parity
      Interspersed
      Parity
      D/Q17
      D/Q0
      D/Q16
      D/Q8
      16
      IDT72T1845/72T1855/72T1865/72T1875/
      72T1885/72T1895 x18 Bus Width
      4666 drw 06
      D/Q17
      D/Q0
      D/Q16
      EMPTY OFFSET (LSB) REGISTER
      Data Inputs/Outputs
      # of Bits Used
      1
      2
      3
      4
      5
      6
      7
      8
      9
      10
      11
      12
      13
      14
      15
      EMPTY OFFSET (MSB) REGISTER
      Data Inputs/Outputs
      17
      16
      18
      1st Parallel Offset Write/Read Cycle
      2nd Parallel Offset Write/Read Cycle
      Data Inputs/Outputs
      3rd Parallel Offset Write/Read Cycle
      4th Parallel Offset Write/Read Cycle
      1
      2
      3
      4
      5
      6
      7
      8
      10
      11
      12
      13
      14
      15
      9
      18 17
      FULL OFFSET (LSB) REGISTER
      1
      2
      3
      4
      5
      6
      7
      8
      9
      10
      11
      12
      13
      14
      15
      16
      1
      2
      3
      4
      5
      6
      7
      8
      10
      11
      12
      13
      14
      15
      9
      FULL OFFSET (MSB) REGISTER
      17
      18
      18 17
      Non-Interspersed
      Parity
      Interspersed
      Parity
      D/Q17
      D/Q0
      D/Q16
      D/Q17
      D/Q0
      D/Q16
      D/Q17
      D/Q0
      D/Q16
      D/Q8
      16
      IDT72T18105/72T18115/72T18125 x18 Bus Width
      5909 drw07
      19
      18
      19
      20
      18
      19
      20
      NOTES:
      1. When programming the IDT72T1895 with an input bus width of x9 and output bus width of x18, 4 write cycles will be required. When Reading the IDT72T1895 with an output
      bus width of x9 and input bus width of x18, 4 read cycles will be required. A total of 6 program/read cycles will be required if both the input and output bus widths are set to x9.
      2. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
      refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
      相關(guān)PDF資料
      PDF描述
      MS3101F24-22SW CONN RCPT 4POS FREE HNG W/SCKT
      IDT723662L12PF8 IC FIFO BI SYNC 8192X36 120QFP
      MAX1093AEEG+T IC ADC 10BIT 250KSPS 24-QSOP
      IDT72V291L20PF IC FIFO SS 32768X36 20NS 64QFP
      ICL3232EIBZ IC 2DRVR/2RCVR RS232 3V 16-SOIC
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
      IDT72T1875L5BB 功能描述:IC FIFO 16384X18 2.5V 5NS 144BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256(64 x 4) 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP(0.300",7.62mm) 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
      IDT72T1875L5BBI 功能描述:IC FIFO 16384X18 2.5V 5NS 144BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256(64 x 4) 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP(0.300",7.62mm) 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
      IDT72T1875L6-7BB 功能描述:IC FIFO 16384X18 6-7NS 144BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256(64 x 4) 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP(0.300",7.62mm) 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
      IDT72T1885L4-4BB 功能描述:IC FIFO 32768X18 2.5V 4NS 144BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256(64 x 4) 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP(0.300",7.62mm) 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
      IDT72T1885L5BB 功能描述:IC FIFO 32768X18 2.5V 5NS 144BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256(64 x 4) 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP(0.300",7.62mm) 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433