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| 型號(hào)： | IDT728985JG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL SW 256X256 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | 7200 |
| 類(lèi)型： | 多路復(fù)用器 |
| 電路： | 1 x 8:8 |
| 獨(dú)立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 其它名稱(chēng)： | 728985JG 800-1994-5 IDT728985JG-ND |
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4
Commercial Temperature Range
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
between the output and input channels; i.e., the throughput delay will be less
than one frame. Table 1 shows the possible delays for the IDT728985 device
in Variable Delay Mode. An example is shown in Figure 3.
CONSTANT DELAY MODE
In this mode frame integrity is maintained in all switching configurations by
making use of a multiple Data Memory buffer technique where input channels
written in any of the buffers during frame N will be read out during frame N+2.
IntheIDT728985,theminimumthroughputdelayachievableinConstantDelay
mode will be 32 time slots; for example, when input time slot 32 (channel 31) is
switched to output time slot 1 (channel 0). Likewise, the maximum delay is
achievedwhenthefirsttimeslotinaframe(channel0)isswitchedtothelasttime
slot in the frame (channel 31), resulting in 94 time slots of delay (see Figure 4).
Tosummarize,anyinputtimeslotfrominputframeNwillbealwaysswitched
to the destination time slot on output frame N+2. In Constant Delay mode the
device throughput delay is calculated according to the following formula:
DELAY=[32+(32-IN)+(OUT-1)]
IN =the number of the input time slot (from 1 to 32)
OUT = the number of the output time slot (from 1 to 32).
MICROPROCESSOR PORT
TheIDT728985microprocessorportis anon-multiplexedbusarchitecture.
Theparallelportconsistsofan8-bitparalleldatabus(D0-D7),sixaddressinput
lines (A0-A5) and four control lines (
CS, DS, R/W and DTA). This parallel
microportallowstheaccesstotheControlRegisters,ConnectionMemoryLow,
ConnectionMemoryHigh,andtheDataMemory. Alllocationsareread/written
except for the Data Memory, which can be read only.
Accesses from the microport to the Connection Memory and the Data
Memory are multiplexed with accesses from the input and output TDM ports.
This can cause variable Data Acknowledge delays (
DTA). In the IDT728985
device, the
DTAoutputprovidesamaximumacknowledgmentdelayof800ns
for read/write operations in the Connection Memory. However, for operations
in the Data Memory (Processor Mode), the maximum acknowledgment delay
can be 1220ns.
SO.TWARE CONTROL
If the A5, A1, A0 address line inputs are LOW then the IDT728985 Internal
Control Register is addressed (see Table 2). If A5 input line is high, then the
remaining address input lines are used to select the 32 possible channels per
input or output stream. As explained in the Control Register description, the
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT728985 Data and
Connect memories. See Figure 6 for accessing internal memories.
The data in the control register consists of Memory Select and Stream
Addressbits,SplitMemoryandProcessorEnablebits(Table3).InSplitMemory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory LOW. The Memory Select bits allow the
Connection Memory High or LOW or the Data Memory to be chosen, and the
StreamAddressbitsdefineinternalmemorysubsectionscorrespondingtoinput
or output streams.
The Processor Enable bit (bit 6) places every output channel on every
output stream in Processor Mode; i.e., the contents of the Connection Memory
LOW(CML,Table5)areoutputontheoutputstreamsonceeveryframeunless
the ODE input pin is LOW. If PE bit is HIGH, then the IDT728985 behaves as
if bits 2 (Channel Source) and 0 (Output Enable) of every Connection Memory
High (CMH) locations were set to HIGH, regardless of the actual value. If PE
is LOW, then bit 2 and 0 of each Connection Memory High location operates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of
theCMLdefinethesourceinformation(streamandchannel)ofthetimeslotthat
is to be switched to an output, Table 4.
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
IfODEisHIGH,thenbit0(OutputEnable)oftheCMHlocationenables(ifHIGH)
or disables (if LOW) for that particular channel.
Thecontentsofbit1(CCO)ofeachConnectionMemoryHighLocation(see
Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/s
output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit on
CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on the
CCO output is transmitted LOW. The contents of the 256 CCO bits of the CMH
are transmitted sequentially on to the CCO output pin and are synchronous to
the TX streams. To allow for delay in any external control circuitry the contents
of the CCO bit is output one channel before the corresponding channel on the
TXstreams. Forexample,thecontentsofCCObitinposition0(corresponding
to TX0, CH0), is transmitted synchronously with the TX channel 31, bit 7. Bit 1's
of CMH for channel 1 of streams 0-7 are output synchronously with TX channel
0 bits 7-0.
INITIALIZATION
Duringthemicroprocessorinitializationroutine,themicroprocessorshould
programthedesiredactivepathsthroughthematrices,andputallotherchannels
intothehighimpedancestate. CareshouldbetakenthatnotwoConnectedTX
outputsdrivethebussimultaneously. TheODEpinshouldbeheldlowonpower
up to keep all output pins in high-impedance. With the CMH setup, the
microprocessor controlling the matrices can bring the ODE signal high to
relinquish high impedance state control to the Connection Memory High bits
outputs.
TABLE 2 ADDRESS MAPPING
A5
A4
A3
A2
A1
A0
LOCATION
0
X
0
Control Register(1)
1
00000
Channel 0(2)
1
00001
Channel 1(2)
1
1
1
1
1
1
11111
Channel 31(2)
TABLE 1 VARIABLE DELAY MODE
Input Channel
Output Channel
Throughput Delay
n
m=n, n+1 or n+2
m-n+32 time slot
n
m>n+2
m-n time slot
n
m<n
32-(n-m) time slot
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| IDT7290820J | 功能描述:IC DGTL SW 2048X2048 84-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - 信號(hào)開(kāi)關(guān)，多路復(fù)用器，解碼器 系列:7200 標(biāo)準(zhǔn)包裝:48 系列:74VHC 類(lèi)型:多路復(fù)用器 電路:4 x 2:1 獨(dú)立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| IDT7290820J8 | 功能描述:IC DGTL SW 2048X2048 84-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - 信號(hào)開(kāi)關(guān)，多路復(fù)用器，解碼器 系列:7200 標(biāo)準(zhǔn)包裝:48 系列:74VHC 類(lèi)型:多路復(fù)用器 電路:4 x 2:1 獨(dú)立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
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