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參數(shù)資料
| 型號(hào)： | IDT728981JG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL SWITCH ST-BUS 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 4:4 |
| 獨(dú)立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1259 (CN2011-ZH PDF) |
| 其它名稱： | 728981JG 800-1505 800-1505-5 800-1505-ND |
3
Commercial Temperature Range
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Data to be output on the serial streams may come from two sources: Data
Memory or Connection Memory. The Connection Memory is 16 bits wide and
is split into two 8-bit blocks—Connection Memory HIGH and Connection
Memory LOW. Each location in Connection Memory is associated with a
particularchannelinanoutputstreamsoastoprovideaone-to-onecorrespon-
dencebetweenConnectionandDataMemories. Thiscorrespondenceallows
for per channel control for each TX output stream.
In Processor Mode, data output on the TX is taken from the Connection
Memory Low and originates from the microprocessor (Figure 2). Where as in
ConnectionMode(Figure1),dataisreadfromDataMemoryusingtheaddress
in Connection Memory. Data destined for a particular channel on the serial
output stream is read during the previous channel time slot to allow time for
memory access and internal parallel-to-serial conversion.
CONNECTION MODE
In Connection Mode, the addresses of input source for all output channels
are stored in the Connection Memory Low. The Connection Memory Low
locationsaremappedtocorresponding8-bitx32-channeloutput. Thecontents
oftheDataMemoryattheselectedaddressarethentransferredtotheparallel-
to-serial converters. By having the output channel to specify the input channel
through the Connection Memory, input channels can be broadcast to several
outputchannels.
PROCESSOR MODE
InProcessorModetheCPUwritesdatatospecificConnectionMemoryLow
locations which are to be output on the TX streams. The contents of the
ConnectionMemoryLowaretransferredtotheparallel-to-serialconverterone
channelbeforeitistobeoutputandaretransmittedeachframetotheoutputuntil
it is changed by the CPU.
CONTROL
The Connection Memory High bits (Table 4) control the per-channel
functionsavailableintheIDT728981.Outputchannelsareselectedintospecific
modes such as: Processor mode or Connection mode and Output Drivers
Enabled or in three-state condition.
OUTPUT DRIVE ENABLE (ODE)
The ODE pin is the master three-state output control pin. If the ODE input
is held LOW all TX outputs will be placed in high impedance regardless
ConnectionMemoryHighprogramming.However,ifODEisHIGH,thecontents
of Connection Memory High control the output state on a per-channel basis.
DELAY THROUGH THE IDT728981
The transfer of information from the input serial streams to the output serial
streamsresultsinadelaythroughthedevice. ThedelaythroughtheIDT728981
devicevariesaccordingtothecombinationofinputandoutputstreamsandthe
movementwithinthestreamfromchanneltochannel. Datareceivedonaninput
stream must first be stored in Data Memory before it is sent out.
As information enters the IDT728981 it must first pass through an internal
serial-to-parallel converter. Likewise, before data leaves the device, it must
passthroughtheinternalparallel-to-serialconverter. Thisdatapreparationhas
an effect on the channel positioning in the frame immediately following the
incoming frame—mainly, data cannot leave in the same time slot. Therefore,
information that is to be output in the same channel position as the information
is input, relative to the frame pulse, will be output in the following frame.
Whether information can be output during a following timeslot after the
information entered the IDT728981 depends on which RX stream the channel
information enters on and which TX stream the information leaves on. This is
causedbytheorderinwhichinputstreaminformationisplacedintoDataMemory
andtheorderinwhichstreaminformationisqueuedforoutput. Table1showsthe
allowableinput/outputstreamcombinationsfortheminimumtwochanneldelay.
5703 drw06
TX
Microprocessor
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
Receive
Serial Data
Streams
5703 drw05
RX
TX
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
Figure 2. Processor Mode
Figure 1. Connection Mode
.UNCTIONAL DESCRIPTION (Cont'd)
Table 1. Input Stream to Output Stream Combinations that can Provide the
Minimum 2-Channel Delay
Input
Output Stream
0
1,2,3
13
Table 2. Address Mapping
NOTES:
1. Writing to the Control Register is the only fast transaction.
2. Memory and stream are specified by the contents of the Control Register.
A5 A4 A3 A2 A1 A0
HEX ADDRESS
LOCATION
0
X
0
00-1F
Control Register(1)
100000
20
Channel 0(2)
100001
21
Channel 1(2)
1
1
111111
3F
Channel 31(2)
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